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dc.contributor.author송용호-
dc.date.accessioned2021-03-09T04:34:05Z-
dc.date.available2021-03-09T04:34:05Z-
dc.date.issued2019-09-
dc.identifier.citationJOURNAL OF SYSTEMS ARCHITECTURE, v. 98, page. 41-52en_US
dc.identifier.issn1383-7621-
dc.identifier.issn1873-6165-
dc.identifier.urihttps://www.sciencedirect.com/science/article/pii/S1383762118306453?via%3Dihub-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/160287-
dc.description.abstractThe rapid development of modern information technology has resulted in a sharp increase in the rate of data growth. This results in a lack of storage space and network bandwidth. Compression technology is typically implemented to mitigate the increasing demand for storage and the transmission cost of data. However, data compression may impose a significant computational burden on the CPU, which results in a degradation of system performance. To solve this problem, a hardware offloading technique can be used. Hardware offloading not only reduces the computational load imposed on the CPU but also improves the performance of the compression algorithm by exploiting hardware parallelism. However, data-hazards associated with the compression algorithm hinders achieving the achievement of a high degree of parallelism. DEFLATE is a widely used lossless compression scheme. Many studies have attempted to eliminate the data dependencies associated with compression algorithms. Unfortunately, existing studies do not address data dependency elimination in Huffman encoding. Our work aims to parallelize Huffman encoding by solving the data-hazard problem in the algorithm. To address the data dependency that exists in the Huffman encoding algorithm, a new data representation for the intermediate data generated during data compression is proposed. The effectiveness of the proposed scheme was evaluated via the implementation of an architecture which applied the approach in the field-programmable gate array (FPGA) platform. Experimental results show that the proposed scheme can increase the throughput of the compressor by up to 14.4%.en_US
dc.description.sponsorshipThis work was supported by the R&D program of MOTIE/KEIT. [10077609, Developing Processor-Memory-Storage Integrated Architecture for Low Power, High Performance Big Data Servers]en_US
dc.language.isoenen_US
dc.publisherELSEVIER SCIENCE BVen_US
dc.subjectData compressionen_US
dc.subjectHuffman codingen_US
dc.subjectAccelerator architectureen_US
dc.subjectField programmable gate arraysen_US
dc.subjectPipeline processingen_US
dc.titleData Dependency Reduction for High-Performance FPGA Implementation of DEFLATE Compression Algorithmen_US
dc.typeArticleen_US
dc.relation.volume98-
dc.identifier.doi10.1016/j.sysarc.2019.06.005-
dc.relation.page41-52-
dc.relation.journalJOURNAL OF SYSTEMS ARCHITECTURE-
dc.contributor.googleauthorKim, Youngil-
dc.contributor.googleauthorChoi, Seungdo-
dc.contributor.googleauthorJeong, Joonyong-
dc.contributor.googleauthorSong, Yong Ho-
dc.relation.code2019040195-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidyhsong-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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