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dc.contributor.author최정욱-
dc.date.accessioned2021-03-08T02:45:28Z-
dc.date.available2021-03-08T02:45:28Z-
dc.date.issued2019-12-
dc.identifier.citationAdvances in Neural Information Processing Systems 32 (NeurIPS 2019), Page. 1-10en_US
dc.identifier.issn1049-5258-
dc.identifier.urihttps://proceedings.neurips.cc/paper/2019/hash/65fc9fb4897a89789352e211ca2d398f-Abstract.html-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/160272-
dc.description.abstractReducing the numerical precision of data and computation is extremely effective in accelerating deep learning training workloads. Towards this end, 8-bit floating point representations (FP8) were recently proposed for DNN training. However, its applicability was only demonstrated on a few selected models and significant degradation is observed when popular networks such as MobileNet and Transformer are trained using FP8. This degradation is due to the inherent precision requirement difference in the forward and backward passes of DNN training. Using theoretical insights, we propose a hybrid FP8 (HFP8) format and DNN end-to-end distributed training procedure. We demonstrate, using HFP8, the successful training of deep learning models across a whole spectrum of applications including Image Classification, Object Detection, Language and Speech without accuracy degradation. Finally, we demonstrate that, by using the new 8 bit format, we can directly quantize a pre-trained model down to 8-bits without losing accuracy by simply fine-tuning batch normalization statistics. These novel techniques enable a new generations of 8-bit hardware that are robust for building and deploying neural network models.en_US
dc.description.sponsorshipThis research is realized by generous collaborations across IBM Research.en_US
dc.language.isoenen_US
dc.publisherNeural Information Processing Systems Foundationen_US
dc.titleHybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networksen_US
dc.typeArticleen_US
dc.relation.page1-10-
dc.contributor.googleauthorSun, Xiao-
dc.contributor.googleauthorChoi, Jungwook-
dc.contributor.googleauthorChen, Chia-Yu-
dc.contributor.googleauthorWang, Naigang-
dc.contributor.googleauthorVenkataramani, Swagath-
dc.contributor.googleauthorSrinivasan, Vijayalakshmi (Viji)-
dc.contributor.googleauthorCui, Xiaodong-
dc.contributor.googleauthorZhang, Wei-
dc.contributor.googleauthorGopalakrishnan, Kailash-
dc.relation.code20190015-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidchoij-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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