Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 이동호 | - |
dc.date.accessioned | 2020-12-10T01:06:53Z | - |
dc.date.available | 2020-12-10T01:06:53Z | - |
dc.date.issued | 2003-07 | - |
dc.identifier.citation | ITC-CSCC : 2003 page.1226 - 1229 | en_US |
dc.identifier.uri | http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01742487 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/156096 | - |
dc.description.abstract | This paper presents an efficient image compression method for memory reduction in multimedia processor which can be simply implemented in hardware and provides high performance. The multimedia processor, which includes processing of high-resolution images and videos, requires large memories: they are external frame memories to store frames and internal line memories for implementing some linear filters. If we can reduce those memories by adopting a simple compression method in multimedia processor, it will strengthen its cost competitiveness. There exist many standards for efficiently compressing images and videos. However, those standards are too complex for our purpose and most of them are 2-D block-based methods, which do not support raster scanned input and output. In this paper, we propose a low-complexity compression method which has good performance, can be implemented with simple hardware logic, and supports raster scan. We have adopted 1x8 Hadamard transform for simple implementation in hardware and compression efficiency. After analyzing the coefficients, we applied an adaptive thresholding and quantization. We provide some simulation results to analyze its performance and compare with the existing methods. We also provide its hardware implementation results and discuss about cost reduction effects when applied in implementing a multimedia processor. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.title | A Low-Complexity Image Compression Method which Reduces Memories Used in Multimedia Processor Implementation | en_US |
dc.type | Article | en_US |
dc.contributor.googleauthor | Jung, Su Woon | - |
dc.contributor.googleauthor | Kim, I Rang | - |
dc.contributor.googleauthor | Lee, Dong-Ho | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | dhlee77 | - |
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