Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김태환 | - |
dc.date.accessioned | 2020-10-20T01:15:19Z | - |
dc.date.available | 2020-10-20T01:15:19Z | - |
dc.date.issued | 2019-10 | - |
dc.identifier.citation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 19, no. 10, Page. 6202-6205 | en_US |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.issn | 1533-4899 | - |
dc.identifier.uri | https://www.ingentaconnect.com/content/asp/jnn/2019/00000019/00000010/art00039;jsessionid=6jqqbc3halnnf.x-ic-live-01 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/154664 | - |
dc.description.abstract | Polysilicon is commonly used as the channel in three-dimensional (3D) NAND flash memory devices. However, degradation of device performance due to grain boundary traps in the channel is a major issue. The saturation on-current level, threshold voltage (V-th), and electron density of 3D NAND flash memory devices with randomly generated grain boundaries were investigated by using three-dimensional technology computer-aided design (TCAD) simulation. The device performance tended to degrade with an increasing number of grains, and the direction of the grains significantly affected the device performance. The large decrease in the electron density of the channel region due to the direction of the grains can be explained according to the formation of the depletion region. | en_US |
dc.description.sponsorship | This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2016R1A2A1A05005502). This work was supported by IDEC (EDA Tool, MPW). | en_US |
dc.language.iso | en | en_US |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | en_US |
dc.subject | Vertical NAND Flash Memory | en_US |
dc.subject | Polysilicon Channel | en_US |
dc.subject | Charge Trapping Layer | en_US |
dc.subject | Threshold Voltage Shift | en_US |
dc.title | Effects of Grain Size on the Electrical Characteristics of Three-Dimensional NAND Flash Memory Devices | en_US |
dc.type | Article | en_US |
dc.relation.no | 10 | - |
dc.relation.volume | 19 | - |
dc.identifier.doi | 10.1166/jnn.2019.17015 | - |
dc.relation.page | 6202-6205 | - |
dc.relation.journal | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.contributor.googleauthor | Lee, Jun Gyu | - |
dc.contributor.googleauthor | Kim, Tae Whan | - |
dc.relation.code | 2019037685 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | twk | - |
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