Design and Automatic Generation of High-Speed Circuits for Wireline Communications

Abstract

This paper introduces key techniques to implement high-speed wireline transceivers presented in [1]-[3]. The frontend equalizers operate at high frequencies by employing energy-efficient current integration and resonant clocking techniques. The baud-rate clock-and-data-recovery (CDR) is implemented to reduce the number of samplers and clock phases for the CDR operation. In addition to the design techniques, the generator-based design methodology [4] [5] is utilized to extremely optimize the sizing parameters of critical circuits by automatically generating their layouts and capturing the layout dependent effects. Two representative design examples that used the proposed techniques achieved 60 Gb/s and 15 Gb/s respectively, which demonstrate their effectiveness to achieve such high data-rates with excellent energy efficiencies.