New Modeling Techniques for Estimation of Power Consumption

Abstract

Low power design of integrated circuits becomes an important issue due to the large scale integration based on deep submicron processing technology. Accurate estimation of power consumption is required in order to effectively design circuits for low power. In this paper, new power modeling techniques are described for static estimation of dynamic power dissipation. Since the dynamic power dissipation is proportional to the signal switching activity, the power dissipation of a circuit is modeled as a function of input signal switching activity. Experimental results show that the estimation errors range from 0 to 22% when second order polynomial expression is used for power modeling.