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dc.contributor.author어영선-
dc.date.accessioned2020-04-13T02:15:09Z-
dc.date.available2020-04-13T02:15:09Z-
dc.date.issued2004-06-
dc.identifier.citation대한전자공학회 학술대회, Page. 435-438en_US
dc.identifier.urihttp://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01715153-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/149405-
dc.description.abstractThis paper presents a new analytical model to suppress RLC resonance effects in power/ground lines due to a decoupling capacitor. First, the resonance frequency of an RLC circuit which is composed of package inductance, decoupling capacitor, and output drivers is accurately estimated. Next, using the estimated resonance frequency, a suitable decoupling capacitor size is determined. Then, a novel design methodology to suppress the resonance effects is developed. Finally, its validity is shown by using 0.18 µm process-based-HSPICE simulation.en_US
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.title공진현상을 감소시키기 위한 효율적인 파워/그라운드 네트 워크 디자인en_US
dc.title.alternativeAn Effective Power/Ground Network Design of VLSI Circuits to Suppress RLC Resonance Effectsen_US
dc.typeArticleen_US
dc.contributor.googleauthor류순걸-
dc.contributor.googleauthor어영선-
dc.contributor.googleauthor심종인-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pideo-
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COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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