Effective Memory Access Optimization by usinng Memory Delay Modeling, Memory Allocation, and Buffer Allocation

Abstract

MPSoCs are gaining popularity because of its potential to solve computationally expensive applications. MPSoCs frequently use two kinds of memories; on-chip SRAMs and off-chip DRAMs. Processors in multicore systems usually take many clock cycles for the transfer of data to/from off-chip memories which affects the overall system performance. While on-chip memory operation takes one or two clock cycles, an off-chip memory access takes significantly more number of clock cycles. Therefore, delay modeling for off-chip memories is important to optimize the overall system performance. It has been known that there are high variations in memory access delays depending on the ways of designing memory configurations and assigning arrays to memories. Furthermore, embedded DRAM technology that provides efficient access modes is actively being developed, possibly becoming a mainstream in future embedded system designs. Memory access delays largely depend on the ways of memory allocation and array binding. An effective technique of memory delay modeling, memory allocation and array binding is proposed. Furthermore, we use buffer allocation for the most frequently accessed arrays to minimize the number of accesses to off-chip DRAMs.