저전력 12 비트 시그마-델타 변조기 설계

Abstract

In this thesis, a new architecture for a low-power second order sigma-delta modulator is proposed. The sigma-delta modulator is a core component that modulates analog signals to digital pulses in telecommunication systems and analog-to-digital converters (ADCs). The sigma-delta modulator archives a very high signal-to-noise ratio (SNR) using oversampling and noise shaping. By reducing the quantization noise power, we were able to improve the resolution and SNR of the sigma-delta modulator. A high oversampling ratio (OSR) reduces the quantization noise power as well as the sampling period, and increases the operating frequency of modulator's internal circuits. The noise shaping property of the sigma-delta modulator modifies the quantization noise distribution to obtain a lower quantization noise power in the signal band frequency. Noise shaping of a high order drastically reduces the quantization noise power and archives a high resolution. However, the high order sigma-delta modulator consumes much power because the number of orders is generally identical to the number of internal amplifiers of the modulator. The proposed circuit implements a second order noise shaping property using only an operational amplifier. Eliminating the operational amplifier, which consumes most power in the modulator, decreases the power consumption of the modulator by half. The proposed modulator is designed for CMOS image sensors with HDTV resolution of 1920 x 1080 pixels operating at 60 frames per second. This modulator has a 12-bit resolution and consumes 270 μW of power during 13μs at a sampling rate of 10 MHz.