능동형 평판 디스플레이를 위한 공핍형의 N형 IGZO TFTs를 이용한 저전력 시프트 레지스터 설계

Abstract

Recently, many researches about oxide thin film transistor (TFT) as a backplane device of active matrix flat panel display (AMFPD) have been reported. The a-IGZO TFT as a kind of the oxide TFT has superior electrical characteristics such as relatively high field effect mobility, high on/off ratio, and good uniformity. Moreover, the a-IGZO TFTs can be fabricated under low temperature and low fabrication cost. Therefore, the a-IGZO TFT has attracted much attention as a next-generation back plane device which can replace hydrogenated amorphous silicon TFT (a-Si:H TFT) and poly crystalline silicon TFT (poly-Si TFT). However, because the a-IGZO TFTs can be operated as only n-type and their threshold voltage (Vth) is negative, it is difficult to fully charge up to high supply voltage level of output signals and achieve low power consumption when digital circuits are designed using the a-IGZO TFTs. To solve these problems, many shift registers have been researched. For fully charging up to high supply voltage level of output signals, most of the shift registers employs the AC-type output stage which connects the clock signal to the drain node of pull-up TFTs of output stage. The shift registers employing AC-type output stage exhibit high power consumption because the capacitive load of clock signals is large due to the large parasitic capacitance of the pull-up TFTs of output stage. In this thesis, a new shift register with low-power consumption and wide voltage swing using a-IGZO TFTs is presented. The proposed shift register is designed for low power by reducing both static and dynamic power consumption. The DC-type output stage in which a power supply voltage is connected to the drain node of pull-up TFTs of output stage rather than a clock signal is applied to the proposed shift register to reduce dynamic power consumption. The DC-type output stage reduces parasitic capacitance of clock signals so that the dynamic power consumption of the clock signals decreases. Moreover, the proposed shift register is driven by only one-clock signal. Therefore, the total dynamic power consumption of clock signals is minimized. Two different power sources are used as low supply voltage levels (-5 V and -10 V) to fully turn off TFTs in main static current path with negative gate-source voltage so that static power consumption can be reduced. In addition, we reduce the duration of short circuit current occurred in a ratioed inverter. According to the measurement results, the proposed shift register successfully works with only one-clock signal. The power consumption of 10 stages is 265 μW at operating frequency of 46.1 kHz and output voltage of 20 V, which is the lowest among previously reported shift registers using oxide TFTs. We proposed driving methods which improves the power consumption and negative Vth range of the shift register by using additional TFTs, and verified these methods with SPICE simulation. According to the simulation results, the power consumption shows a decrease of 54 % and the advanced shift register successfully works even though the Vth of TFTs negatively shifts to -3.7 V.