Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 정정화 | - |
dc.contributor.author | 안병규 | - |
dc.date.accessioned | 2020-03-10T01:17:09Z | - |
dc.date.available | 2020-03-10T01:17:09Z | - |
dc.date.issued | 2012-08 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/135955 | - |
dc.identifier.uri | http://hanyang.dcollection.net/common/orgView/200000419959 | en_US |
dc.description.abstract | 물리적인 한계에 직면한 반도체 집적 공정의 한계를 극복하고, 지속적으로 무어의 법칙에 맞춰 집적도를 향상시키기 위한 방법으로 through-silicon via (TSV) 기술을 이용한 3차원 집적회로(3D IC)가 최근 각광을 받고 있다. TSV 기술은 기존에 사용되던 와이어 본딩 기술에 비해서 가장 짧은 전기적 배선을 제공할 뿐만 아니라, 전기적 기생 성분을 줄여서 전체 시스템의 성능을 큰 폭으로 개선한다. 하지만, TSV에 기반한 3D IC의 설계는 아직 해결되지 못한 많은 어려운 문제들이 있으며, 그 중에서도 전원 공급 네트워크 합성은 가장 중요한 문제 중 하나로 인식되고 있다. 특히, IR-drop 제한 조건을 만족시키면서, 전원 bump와 전원 TSV를 이용해서 3차원으로 적층된 IC의 모든 부분에 원활히 전원을 전달하는 것은 매우 어려운 과제이다. 그리고, 3D 전원 공급 네트워크에 사용된 전원 TSV의 개수는 스탠더드 셀의 배치/배선 혼잡을 예방하기 위해서 제한되어야 하며, 전원 TSV와 신호 배선 사이에서 발생되는 coupling noise는 전체 시스템의 성능 저하를 야기하기도 한다. 따라서, 이러한 문제를 해결하기 위하여, 3D 전원 공급 네트워크를 분석, 합성 및 최적화하는 연구가 반드시 필요하다. 본 논문에서는 3D IC에서 최적의 전원 공급 네트워크를 합성하기 위하여 새로운 모델링 및 분석 기법을 개발하고, IR-drop에 영향을 주는 요인들에 대해서 분석한다. 그리고 3D 전원 공급 네트워크에서 IR-drop 문제를 해결하는 새로운 방법론을 제안한다. 본 논문의 주요 기여도는 다음과 같다. 첫 번째, 본 논문에서는 SPICE의 정확도를 가지는 3D 전원 공급 네트워크 모델링 및 분석 기법을 제안한다. 두 번째, 전원 bump와 전원 TSV의 개수와 위치가 3D 전원 공급 네트워크의 IR-drop에 미치는 영향을 조사한다. 세 번째, 본 논문에서는 IR-drop 조건 5%을 만족하면서 전원 bump와 전원 TSV의 개수를 동시에 최소화하는 효율적인 배치 알고리즘을 제안한다. 네 번째, 3D IC에서 전원 공급 망의 폭과 간격이 전원 bump와 전원 TSV에 개수에 미치는 영향에 대해서 조사하고, 제한된 배선 리소스 조건하에서 전원 bump와 전원 TSV 개수를 최소화하는 점진적인 전원 공급 망 개선 기법을 제안한다. 마지막으로, 전원 공급을 보다 안정화 시키기 위해서 전체 전원 공급 네트워크에서의 IR-drop 편차를 최소화하는 알고리즘을 제안한다. 본 논문에서 제안된 최적화 기법들은 C++/STL 프로그래밍 언어로 구현되었고, 다양한 실험 결과를 통해서 제안한 방법론이 기존 방법론에 비하여 효과적임을 증명하였다.|Because the semiconductor fabrication faces physical limitations, thorough-silicon via (TSV) based three-dimensional integration circuit (3D IC) is emerging as the breakthrough technology to follow in a series of the Moore’s Law. The TSV technology brings the performance improvement through the minimization of wire length and electrical parasitics as compared to the conventional wire bonding technology. However, there are many unresolved challenges in the area of physical design for TSV-based 3D ICs. Power delivery network synthesis is recognized as one of the biggest challenges in the industry. It is highly difficult to deliver power to every part of 3D stacked dies by using the power bumps and power TSVs, while meeting the tight IR-drop constraints. The number of TSVs used in the 3D power network is also limited so as to prevent placement/routing congestion of standard cell. In addition, the coupling noise between P/G TSVs and signal wires may lead to performance degradation in overall system. Those intricate and unresolved problems led this work to an extensive further study on analysis, synthesis, and optimization of power delivery network. The main contributions of this dissertation are as follows. First, new modeling and analysis techniques for 3D power network are presented with a SPICE-accuracy. Second, the impact of the number of power bumps and TSVs on the IR-drop is investigated in the 3D ICs. Third, an effective co-placement algorithm is proposed to minimize the number of power bumps and TSVs while meeting 5% IR-drop constraints. Fourth, the impact of the width and pitch of power mesh on the number of power bumps and TSVs is examined in the 3D ICs. The incremental power mesh improvement techniques are presented to minimize the number of power bumps and TSVs under limited routing resource. Finally, to stabilize the power supply more, a novel IR-drop variation minimization algorithm is presented in overall power delivery network. The proposed optimization techniques have been implemented in C++/STL programming language. The various experimental results show that they are more capable in their design productivity, compatible in current industry, and reliable with power delivery network compared to conforming studies.; Because the semiconductor fabrication faces physical limitations, thorough-silicon via (TSV) based three-dimensional integration circuit (3D IC) is emerging as the breakthrough technology to follow in a series of the Moore’s Law. The TSV technology brings the performance improvement through the minimization of wire length and electrical parasitics as compared to the conventional wire bonding technology. However, there are many unresolved challenges in the area of physical design for TSV-based 3D ICs. Power delivery network synthesis is recognized as one of the biggest challenges in the industry. It is highly difficult to deliver power to every part of 3D stacked dies by using the power bumps and power TSVs, while meeting the tight IR-drop constraints. The number of TSVs used in the 3D power network is also limited so as to prevent placement/routing congestion of standard cell. In addition, the coupling noise between P/G TSVs and signal wires may lead to performance degradation in overall system. Those intricate and unresolved problems led this work to an extensive further study on analysis, synthesis, and optimization of power delivery network. The main contributions of this dissertation are as follows. First, new modeling and analysis techniques for 3D power network are presented with a SPICE-accuracy. Second, the impact of the number of power bumps and TSVs on the IR-drop is investigated in the 3D ICs. Third, an effective co-placement algorithm is proposed to minimize the number of power bumps and TSVs while meeting 5% IR-drop constraints. Fourth, the impact of the width and pitch of power mesh on the number of power bumps and TSVs is examined in the 3D ICs. The incremental power mesh improvement techniques are presented to minimize the number of power bumps and TSVs under limited routing resource. Finally, to stabilize the power supply more, a novel IR-drop variation minimization algorithm is presented in overall power delivery network. The proposed optimization techniques have been implemented in C++/STL programming language. The various experimental results show that they are more capable in their design productivity, compatible in current industry, and reliable with power delivery network compared to conforming studies. | - |
dc.publisher | 한양대학교 | - |
dc.title | TSV와 Bump를 사용한 3차원 집적회로의 전원 공급 네트워크 최적화 | - |
dc.title.alternative | Optimization of Power Delivery Network for 3D ICs with TSV and Bump | - |
dc.type | Theses | - |
dc.contributor.googleauthor | 안병규 | - |
dc.contributor.alternativeauthor | Byung-Gyu Ahn | - |
dc.sector.campus | S | - |
dc.sector.daehak | 대학원 | - |
dc.sector.department | 전자컴퓨터통신공학과 | - |
dc.description.degree | Doctor | - |
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