A Study on resistance Variation and Stochastic Macro-Modeling of MTJ Resistance Variation for STT-MRAM
- Title
- A Study on resistance Variation and Stochastic Macro-Modeling of MTJ Resistance Variation for STT-MRAM
- Author
- 최준태
- Advisor(s)
- 송윤흡
- Issue Date
- 2015-02
- Publisher
- 한양대학교
- Degree
- Master
- Abstract
- STT-MRAM is one of the most promising candidates for the next generation universal memory to replace DRAM because of to its non-volatility, high density, high speed and low power consumption [1,2]. A STT-MRAM is contains a structure called magnetic tunnel junction (MTJ), which is consisted with pinned ferromagnetic layer, free (switching) ferromagnetic layer and a thin tunnel oxide barrier between them. The resistance of MTJ depends on magnetization of two ferromagnetic layers, which is called parallel (RP) and anti-parallel states (RAP). The resistance difference between two states is called tunneling magneto-resistance ratio (TMR) [3, 4]. Recently, many researches on STT-MRAM sensing circuits using self-reference scheme has been proposed [7-29]. However, self-reference sensing circuits take relatively long reading time as they need reading process twice. Also, conventional reading scheme requires an accurate comparable resistance value to determine whether the MTJ is parallel and anti-parallel states. However, the resistance of MTJ has dependent characteristics on parameters such as oxide thickness (tox), surface (A), temperature (T), and bias voltage (Vb) [30-37]. Variation of these parameters could cause serious resistance variation, which could lead read failure. Moreover, an accurate macro-model of MTJ characteristic is required for more reliable design of sense circuit for STT-MRAM. There have been many researches on the macro-model of MTJ for simulation, but they are not able to consider the parameter variation and stochastic behavior of MTJ resistance [40-50]. In this paper, we investigated on the effect of tox, A, T and Vb. We also propose a stochastic macro-model of MTJ resistance considering oxide thickness, surface area, temperature, and bias voltage variation with Monte-Carlo using Verilog-A language.
- URI
- https://repository.hanyang.ac.kr/handle/20.500.11754/129092http://hanyang.dcollection.net/common/orgView/200000425667
- Appears in Collections:
- GRADUATE SCHOOL[S](대학원) > ELECTRONICS AND COMPUTER ENGINEERING(전자컴퓨터통신공학과) > Theses (Master)
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