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dc.contributor.advisorSung-ju Park-
dc.contributor.author조준형-
dc.date.accessioned2020-02-25T16:30:44Z-
dc.date.available2020-02-25T16:30:44Z-
dc.date.issued2015-02-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/128688-
dc.identifier.urihttp://hanyang.dcollection.net/common/orgView/200000425849en_US
dc.description.abstractAs the use of portable devices increases, the usage of NAND flash memory The degree of integration of the NAND flash memory has also increased exponentially. To increase even failure occurrence frequency in accordance with an increase in the memory capacityvarious Error Correcting Code (ECC) techniques have been. his, reus the spare cell that not used after the production of the memory. As you increase the ECC check bit, the failure rate is reduced, the treatment time was confirmed to be reduced.-
dc.publisher한양대학교-
dc.titlePerformance Improvement of Memory Error Correcting Code by Utilizing Spare Memory Cells.-
dc.typeTheses-
dc.contributor.googleauthorJoon-hyeong Jo-
dc.sector.campusS-
dc.sector.daehak대학원-
dc.sector.department컴퓨터공학과-
dc.description.degreeMaster-
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GRADUATE SCHOOL[S](대학원) > COMPUTER SCIENCE & ENGINEERING(컴퓨터공학과) > Theses (Master)
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