A research about constructing the universal MTJ logic gates which represent 16 binary Boolean logic operations and Full-adder built by cascading logic gates

Abstract

The magnetic tunnel junction (MTJ) has been renowned for being one of the most suitable candidates for beyond complementary metal oxide semiconductor (CMOS). Its properties such as non-volatility, high speed, and zero standby power have gained much attention from industries and academia. As a matter of fact, MTJ has been replaceable for conventional memory technology which consumes a significantly high static power as it continues to scale down. Thus, many studies have progressed to sustain its use to develop MTJ-based memory (e.g. STT-MRAM) practical and marketable. On the other hand, a relatively few researches have achieved practical logic applications which infers that the MTJ’s simple resistor like structure makes it difficult to implement unlike the application of memory. In this work, we present MTJ logic cell with 3 terminals operated by the application of external magnetic field and voltage bias. The complementary of both inputs produces 7 binary Boolean logic operations. Additionally, 3 supplementary circuits have been employed to form the structure of universal MTJ logic gate which allows 16 logic operations (a complete set of two input-based Boolean logic operations) to perform in just one logic stage. This completeness could make a logic design simpler because each MTJ logic gate is considered as a building block, so only a gate-level design is allowed without considering the lower abstraction level. Mixed simulations with a compact model have verified all of the operations. In order to accomplish more complex logic operations such as an arithmetic function, a full-adder (FA) circuit has been chosen as an example and constructed by the MTJ logic gates in 2 ways: a conventional design with 5 gates and an advanced design with 2 gates. The reduced gate counts in the latter are achieved by the reconfigurable capability which is a major advantage of the universal MTJ logic gate. The power consumptions have also been analyzed for those designs to compare with conventional CMOS-based FA as a reference. Considering the universal logic gate in this thesis as a pioneer, we are still finding a way to enhance the performance and to apply an efficient non-volatile logic algorithm. We believe that these efforts can accelerate the utilization of the MTJ logic gates for practical applications and partly replace the conventional logic gates where the efficiency is well appreciated.