이중 모드 디지털 클럭 및 데이터 복원 회로

Abstract

A 6-Gbps dual-mode fully-digital clock and data recovery (CDR) circuit for both the forwarded clocking system and the reference-less clocking system has been developed. In the forwarded clocking mode, proposed dual-mode CDR operates as phase rotating phase locked loop (PLL). In order to mitigate drawbacks of the analog PLL and the digital PLL, hybrid PLL is used. In the reference-less clocking mode, proposed CDR has two-step operation which are initial frequency training and the normal operation. Fabricated in a 65-nm CMOS technology, the prototype consumes 25.2 and 22.8-mW from 1.2-V supply and root-mean-square (RMS) jitter of the recovered clock was measured to be 7.2 and 8.5-ps for 6-Gbps forwarded clocking system and reference-less clocking system, respectively. For both operation modes, less than 10-12 bit-error-rate (BER) was achieved with 27-1 pseudo-random binary sequence (PRBS) pattern and active area of the implemented CDR circuit is 0.025-mm2.