Low-Power and Area-Efficient Reconfigurable Transceiver for 3-D Ultrasound Imaging Systems

Abstract

3차원 초음파 영상 시스템은 인체 기관과 조직에 대한 체적 이미지 및 임의 방향에 대한 2차원 단면 이미지를 제공하기 때문에 임상 진단 및 의료 개입에서 사용이 증가하고 있다. 최근 3차원 초음파 영상 시스템은 2차원 배열된 수 천개의 초음파 트랜스듀서로 기반의 2차원 초음파 프로브를 요구 한다. 하지만 수 천개의 초음파 트랜스듀서를 집적하고 출력 신호를 처리하는데 있어서 기술적 어려움이 있다. 먼저 2차원 배열을 구현하기 위해서는 좁은 면적의 초음파 트랜스듀서 아래에 송수신 회로를 집적해야 한다. 또한, 초음파 프로브의 경우 피부와 직접적으로 접촉하기 때문에 송수신 회로의 발열로 인한 열상을 방지하기 위해서 저전력 송수신 회로가 필요하다. 뿐만 아니라 수 천개의 초음파 트랜스듀서에서 출력되는 신호를 처리하기 위해서는 다양한 배열 제어 처리 방법을 적용하여 영상화하고자하는 기관이나 조직에 따라 영상의 신호 잡음비 (signal-to-noise ratio) 및 프레임 속도 (frame rate)를 조절할 수 있는 송수신 회로가 필요하다. 이러한 기술적 과제를 해결하기 위해서 본 논문에서는 축전식 미세 가공 초음파 트랜스듀서(capacitive micro-machined ultrasonic transducer) 배열 아래 가변구조형 송수신 회로 배열을 집적한 프론트 엔드 집적회로 (front-end IC), 유동 제어 회로 (floating control circuit) 를 이용한 소 면적 고전압 보호 스위치 및 감쇠 적응 잡음 제어 (attenuation-adaptive noise contrl)를 이용한 저전력 저 잡음 증폭기 제안하였다. 첫번째로, 면적을 줄이기 위하여 유동 제어 회로를 이용한 고전압 보호 스위치를 제안하였다. 제안 된 고전압 보호 스위치는 수동 소자없이 3개의 MOSFET과 3개의 LDMOSFETs 구성되어 있다. 2차원 배열된 고전압 보호 스위치의 모든 제어 신호를 공유함으로써 신호의 배선 복잡도를 줄일 수 있다. 제안 된 고전압 보호 스위치는 0.18μm 50 V Bipolar-CMOS-DMOS (BCD) 공정을 사용하여 제작하였으며 그 면적은 85 × 65μm2이다. 입력 신호 주파수와 출력 전압 진폭은 각각 5 MHz와 0.9 Vpp 일 때 측정 된 2차 고조파 왜곡은 -55 dB 이며 오프 절연(off-isolation)은 -53 dB으로 측정되었다. 두번째로, 전력 소모 감소를 위하여 감쇠 적응 잡음 제어 기법을 이용한 저 잡음 증폭기를 제안하였다. 제안된 감쇠 적응 잡음 제어 기법은 초음파의 감쇠에 따라 잡음 레벨을 제어하여 낮은 깊이에서의 불필요한 잡음 레벨로 인하여 발생하는 불필요한 전력 소비를 줄일 수 있다. 또한 전류 피드백을 이용한 증폭기를 사용함으로써 감쇠 적응 잡음 제어 기법으로 인한 폐쇄 루프 이득과 대역폭을 변화를 최소화하였다. 제안 된 저 잡음 증폭기는 0.18μm CMOS 공정을 이용하여 제작하였다. 제작된 저 잡음 증폭기는 입력 기준 전압 잡음 밀도는 5 MHz에서 1.01 nV / √Hz 이다. 2차 고조파 왜곡은 입력 신호의 주파수와 출력 전압 진폭은 각각 5 MHz와 2 Vpp 일 때 -53.5 dB 이다. 저 잡음 증폭기의 전력 소모는 1.8 V 전원에서 16.2 mW이며 감쇠 적응 잡음 제어 기법을 적용하였을 경우 저 잡음 증폭기의 소비 전력은 적용하지 않았을 때에 비하여 64 %로 감소하였다. 제안된 저 잡음 증폭기의 잡음 효율 계수(noise efficiency factor)는 3.69이며 기존의 저 잡음 증폭기와 비교하여 가장 낮은 잡음 효율 계수를 갖는다. 마지막으로, 다양한 배열 처리 방법을 적용하기 위해서 16 × 16 배열의 재구성 가능한 송수신 회로를 집적한 프런트 엔드 집적회로를 제안하였다. 제안된 프론트 엔드 집적 회로는 용도에 따라 이미지의 신호 잡음비과 프레임 속도를 최적화할 수 있다. 또한 각 축전식 미세 가공 초음파 트랜스듀서 아래에 재구성 가능한 송수신 회로를 집적하기 위해 디지털 펄스 제어 회로와 소면적 고전압 펄스 송신 회로를 제안하였다. 제안된 프론트 엔드 집적회로는 실리콘 기반의 micro-electro-mechanical system (MEMS) 공정과 0.35μm 120 V BCD 공정을 이용하여 제작하였다. 모든 초음파 트랜스듀서를 사용하는 송수신 배열 패턴을 이용하여 1mm 직경 스프링의 3차원 이미지를 성공적으로 획득하였다. |Three-dimensional (3-D) ultrasound imaging systems provide the volumetric and 2-D cross-sectional images at arbitrary orientation of organs and tissues, and thus are increasingly used in clinical diagnosis and medical intervention. To implement 3-D ultrasound imaging systems, a 2-D ultrasound probe consisting of a 2-D array of thousands of ultrasound transducers is demanded. However, several technical challenges exist in integrating thousands of ultrasound transducers and processing the output signals generated from them. To implement the 2-D array, a transceiver should be integrated underneath each ultrasound transducer occupying a small area which is determined by the space sampling law and also should have low power consumption to protect the skin from heat. Moreover, to process the output signals from thousands of ultrasound transducers, the transceiver should be able to control the transmitting and receiving array patterns with different image SNR and frame rate so as to adopt various array processing methods according to the application. To overcome these technical challenges, this dissertation proposes a front-end IC integrating a reconfigurable transceiver array underneath a capacitive micro-machined ultrasonic transducer (CMUT) array and low-power area-efficient sub-circuits, which include a high-voltage (HV) protection switch employing a floating control circuit and a low noise amplifier using attenuation-adaptive noise control for the reconfigurable transceiver. First, an HV protection switch which adopts a floating control circuit is proposed to reduce the area by reducing the number of laterally diffused MOSFETs (LDMOSFETs) and removing the passive components such as capacitors and resistors. The proposed HV protection switch is composed of three MOSFETs and three LDMOSFETs without any passive components. Moreover, the signal routing complexity of control signals is reduced by sharing all control signals in the 2-D array of the HV protection switches. The proposed HV protection switch was fabricated using a 0.18 μm 50 V BCD process and occupies an area of 85 × 65 μm2. The measured 2nd harmonic distortion is -55 dB when the input signal frequency and output voltage swing are 5 MHz and 0.9 Vpp, respectively. The off-isolation is also measured to be -53 dB. Second, a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) is proposed to reduce power consumption. The proposed AANC reduces unnecessary power consumption, which arises from useless noise floor at low-depth, by adjusting the noise floor according to the attenuation of ultrasound. In addition, a current feedback topology minimizes variations of the closed loop gain and bandwidth, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-μm CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 nV/√Hz at 5 MHz. The 2nd harmonic distortion is measured to be -53.5 dB when the input signal frequency and output voltage swing are 5 MHz and 2 Vpp, respectively. The power consumption of the LNA with the AANC is 16.2 mW at a supply voltage of 1.8 V, which is reduced to 64 % of that without the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69 which is the lowest NEF compared with previously reported LNAs for ultrasound imaging. Finally, a front-end IC employing a reconfigurable 16 × 16 transceiver array is proposed to configure the transmitting and receiving array patterns for various array processing methods that can optimize the image SNR and frame rate according to the application. The proposed area-efficient HV pulse transmitter with digital pulse controller enables to integrate a transceiver underneath each CMUT. The proposed front-end IC was fabricated using a silicon-based micro-electro-mechanical system (MEMS) process and a 0.35 μm 120 V Bipolar-CMOS-DMOS (BCD) process. The 3-D image of a spring with a diameter of 1 mm was successfully acquired using the proposed front-end IC with fully transmitting and receiving array patterns.; Three-dimensional (3-D) ultrasound imaging systems provide the volumetric and 2-D cross-sectional images at arbitrary orientation of organs and tissues, and thus are increasingly used in clinical diagnosis and medical intervention. To implement 3-D ultrasound imaging systems, a 2-D ultrasound probe consisting of a 2-D array of thousands of ultrasound transducers is demanded. However, several technical challenges exist in integrating thousands of ultrasound transducers and processing the output signals generated from them. To implement the 2-D array, a transceiver should be integrated underneath each ultrasound transducer occupying a small area which is determined by the space sampling law and also should have low power consumption to protect the skin from heat. Moreover, to process the output signals from thousands of ultrasound transducers, the transceiver should be able to control the transmitting and receiving array patterns with different image SNR and frame rate so as to adopt various array processing methods according to the application. To overcome these technical challenges, this dissertation proposes a front-end IC integrating a reconfigurable transceiver array underneath a capacitive micro-machined ultrasonic transducer (CMUT) array and low-power area-efficient sub-circuits, which include a high-voltage (HV) protection switch employing a floating control circuit and a low noise amplifier using attenuation-adaptive noise control for the reconfigurable transceiver. First, an HV protection switch which adopts a floating control circuit is proposed to reduce the area by reducing the number of laterally diffused MOSFETs (LDMOSFETs) and removing the passive components such as capacitors and resistors. The proposed HV protection switch is composed of three MOSFETs and three LDMOSFETs without any passive components. Moreover, the signal routing complexity of control signals is reduced by sharing all control signals in the 2-D array of the HV protection switches. The proposed HV protection switch was fabricated using a 0.18 μm 50 V BCD process and occupies an area of 85 × 65 μm2. The measured 2nd harmonic distortion is -55 dB when the input signal frequency and output voltage swing are 5 MHz and 0.9 Vpp, respectively. The off-isolation is also measured to be -53 dB. Second, a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) is proposed to reduce power consumption. The proposed AANC reduces unnecessary power consumption, which arises from useless noise floor at low-depth, by adjusting the noise floor according to the attenuation of ultrasound. In addition, a current feedback topology minimizes variations of the closed loop gain and bandwidth, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-μm CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 nV/√Hz at 5 MHz. The 2nd harmonic distortion is measured to be -53.5 dB when the input signal frequency and output voltage swing are 5 MHz and 2 Vpp, respectively. The power consumption of the LNA with the AANC is 16.2 mW at a supply voltage of 1.8 V, which is reduced to 64 % of that without the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69 which is the lowest NEF compared with previously reported LNAs for ultrasound imaging. Finally, a front-end IC employing a reconfigurable 16 × 16 transceiver array is proposed to configure the transmitting and receiving array patterns for various array processing methods that can optimize the image SNR and frame rate according to the application. The proposed area-efficient HV pulse transmitter with digital pulse controller enables to integrate a transceiver underneath each CMUT. The proposed front-end IC was fabricated using a silicon-based micro-electro-mechanical system (MEMS) process and a 0.35 μm 120 V Bipolar-CMOS-DMOS (BCD) process. The 3-D image of a spring with a diameter of 1 mm was successfully acquired using the proposed front-end IC with fully transmitting and receiving array patterns.