A Study on Optimum High Frequency Switch Circuit Design Methodologies

Abstract

본 논문에서는 아래의 3가지 주제에 관한 연구가 수행되었다.

1. 실제 PA robustness test 에서 사용 가능한 규칙적인 전자식 임피던스 튜너

2. 고주파 스위치 장치로써 최근 주목받고 있는 CMOS SOI(Silicon-on-insulator) 공정 기반의 향상된 전력운용용량의 고주파 스위치의 설계방법론 (튜너의 핵심 소자인 스위치 소자의 비선형성 분석)

3. 94 GHz 이상 밀리미터파 고성능 스위치

최근 모바일 장비들의 비약적인 발전은 모바일용 하드웨어 제조업체들로 부터 모바일 전력증폭기를 포함하는 고성능 프론트-엔드 모듈(Front-end module, FEM)에 대한 수요를 증가시켰다. FEM 개발을 위해 사용되는 핵심장비인 임피던스 튜너는 용도에 따른 전력증폭기의 입출력 임피던스 정합조건을 파악(PA source/load-pull test)하고 제작된 FEM의 출력단에서 부정합 상태의 안테나 부하를 임의로 구현하여 FEM 성능 변화를 관찰하는 장비로써, 고성능 임피던스 튜너에 대한 하드웨어 제조업체들의 수요는 상당하다. 그러나 산업체에서 주로 사용되는 기존의 기계식 임피던스 튜너는 느린 동작속도와 큰 부피, 높은 장비가격으로 인해 전력증폭기 의 개발시간 및 비용을 증가시킨다. 이러한 문제해결을 위해 고속, 소형, 낮은 장비가격을 장점으로 갖는 규칙적인 임피던스 구현이 가능한 전자식 임피던스 튜너를 제안하고 그 동작을 검증하였다.

기존 기계식 임피던스 튜너의 대안으로 다양한 전자식 임피던스 튜너들이 보고되어 왔으나 제안된 회로 토폴로지의 한계 및 스위치 소자의 제한된 ON-특성(삽입손실) 및 OFF-특성(격리도)으로 인해 규칙적인 임피던스 구현이 어렵다는 치명적인 단점이 있었다. 따라서, 본 연구에서는 3-dB 90도 결합기의 신호 전달 및 반사 특성을 이용하여 규칙적인 임피던스 구현이 가능한 전자식 임피던스 튜너를 제안하였다. 제안된 전자식 임피던스 튜너는 총 3가지 형태로 2개의 주요 회로 토폴로지와 스위치 소자로써 PIN diode 및 CMOS SOI FET-switch 를 사용하여 제작되었다. 고속 및 소형의 이점을 취하며 높은 SWR 운용범위를 확보하기 위한 다양한 회로기술이 적용되었으며, 최종적으로 2~6 의 SWR 범위 내에서 총 24개의 위상변화를 갖고 저주파수(700 – 915 MHz) 및 중간주파수 (1.7 – 2.025 GHz) 대역에서 동작 가능한 전자식 임피던스 튜너모듈이 제작되었다. 제작된 임피던스 튜너는 시뮬레이션 결과와 비교하여 SWR = 2.5 / 6 에서 매우 균일한 0.001/0.006 의 반사계수 및 5º 이내의 위상 편차를 갖으며 (PIN diode 형 임피던스 튜너, Ver.2), 규칙적인 임피던스 구현이 가능하기 때문에 실제적인 PA 견고성 측정용 장비로써 활용가능하다. 제안된 튜너의 효용성을 검증하기 위해 PIN diode 형 임피던스 튜너를 (Ver.2) 사용하여 저주파대역 PA 견교성 측정이 SWR = 6 조건하에서 수행되었다. 기존 상용 기계식 튜너와 비교하여 제안된 튜너는 SWR =6 및 Pin = 20 dBm 의 조건하에서 0.9 dB 이득 및 3 dB 이내의 ACLR 편차를 보인다. 또한, PIN diode 형 임피던스 튜너들은 (Ver.1 및 2) Pin = 20 dBm 이내에서 PA 견고성 측정이 가능하나, CMOS SOI FET-스위치를 사용한 임피던스 튜너의 경우 (Ver.3) 26 dBm 의 높은 전력운용용량을 갖는다.

다음으로 본 논문의 연구주제는 자연스럽게 임피던스 튜너의 핵심소자인 스위치 소자로 연계되었으며, 최근 고주파 스위치 공정으로 주목받고 있는 CMOS SOI 공정 기반의 고주파 스위치의 전력운용용량 향상을 위한 회로 토포로지를 제안하고 검증하였다. 기존의 8단 적층된 단일입력 및 출력 (Single-Pole Single-Throw, SPST) 스위치와 비교하여 전력운용용량을 향상시킨 7단 적층된 단일입력 및 출력 스위치가 제안되었으며, 각각 2 GHz 에서 0.213 dB 및 0.189 dB 의 삽입손실과 38.6 dBm 및 38.5 dBm 의 전력운용용량을 확보하였다. 이는 전력운용용량의 하락 없이 약 11%의 삽입손실 성능향상 효과를 확보한 결과이다.

마지막으로 최근 상용화되고 있는 5세대 (5G) 통신기술의 발전추세를 고려하여 밀리미터파용 저손실 및 고전력운용용량 스위치 회로 토폴로지를 제안하고 검증하였다. 제안된 단일입력 및 출력 스위치는 직렬 스위치 블록 없이 2단 적층된 병렬 스위치 블록만으로 구성되어 94 GHz 에서 1.76 dB 의 낮은 삽입손실 및 스위치 ON-상태에서 19.5 dBm 이상의 높은 전력운용용량을 확보하였고, 총 4개의 서로 다른 크기의 병력 스위치 블록 분로를 통해 30.75 dB 이상의 높은 격리도 및 스위치 OFF-상태에서 향상된 전력운용용량을 확보하였다.

|In this dissertation, the following three subject were studied.

1. A programmable electronic impedance tuner available in practical PA robustness test.

2. Improved power handling capability RF switch design methodology based on CMOS SOI (Silicon-on-insulator) process, which has recently attracted attention as a RF switch device.

3. High-performance millimeter-wave switch over 94 GHz.

Recent rapid advances in mobile devices have increased demand for high-performance front-end modules (FEMs), including mobile power amplifiers (Pas), from mobile hardware manufacturers. The impedance tuner is a key equipment used for FEM development to find the input/output impedance matching conditions of the power amplifier according to the application (PA source/load-pull test) and to observe the FEM performance change by arbitrarily implementing the mismatched antenna conditions at the output stage of the fabricated FEM. And the hardware manufacturers’ demand for high performance impedance tuners is substantial. However, conventional mechanical impedance tuners used typically in industry increase the development time and cost of the PA due to slow operation speed, bulky size, and expensive equipment. To solve these problems, a programmable electronic impedance tuner having advantages of fast speed, small size and cost-effective has been proposed and its operation has been verified.

Various electronic impedance tuners have been reported as an alternative to conventional mechanical impedance tuners. However, these impedance tuners have a critical fault that makes it difficult to implement a uniform impedance distribution due to the limitations of the proposed circuit topology and the restricted ON/OFF-state characteristic (insertion loss/isolation) of the switch devices. Therefore, an electronic impedance tuner has been proposed that can implement uniform impedance distribution by using transission and reflection characteristics of a 3-dB 90 degree coupler. The proposed electronic impedance tuner was fabricated in three modules by using two main circuit topologies, and a PIN diode and a CMOS SOI FET-switch were used as switch devices. Various circuit technologies have been applied to ensure high SWR coverage while maintaining the advantage of high speed and small size. Ultimately, an electronic impedance tuner with a total of 24 phase variation in SWR = 2 to 6 and operating in the low-band (700 – 915 MHz) and mid-band (1.7 – 2.025 GHz) was fabricated. The fabricatd tuner showed very uniform reflection coefficient distribution with magnitude deviations of less than 0.001 / 0.006 at SWR = 2.5 / 6 and phase deviations of less than 5º. (PIN diode-type tuner, Ver.2). The proposed tuner can be used as a practical PA robustness test equipment because it can implement uniform impedance distribution. To verify the usefulness of the proposed tuner, a low-band PA robustness measurement under SWR = 6 was performed using the proposed PIN diode type impedance tuner(Ver.2). Measured results showed that the proposed tuner was in accord with the commercial mechanical tuner, showing gain deviations of less than 0.9 dB and ACLR deviations of less than 3 dB at SWR = 6 at Pin=20 dBm. The power handling capability of the PIN diode type impedance tuners(Ver.1 and 2) are limitated up to Pin = 20 dBm. However, an electronic impedance tuner using a CMOS SOI FET-switch (Ver.3) has a high power handling capability of 26 dBm.

Next, the study topic was naturally changed with the switch device which is the key component of the electronic impedance tuner. A circuit topology of the improved power handling capability RF switch based on CMOS SOI process which attracted attention as process for high performance RF switch has been proposed and verified. A 7-stacked SPST (Single-Pole Sing-Throw) switch with improved power handling capability compared to conventional 8-stacked SPST switches has been proposed. Measured results showed the insertion loss performance of 0.213 / 0.189 dB and the power handling capability of 38.6 / 38.5 dBm at 2 GHz in the conventional 8-staced switch and the proposed 7-stacked switch respectively. This is a result of the improved insertion loss about 11% without power handling capability degradation.

Lastly, the circuit topologies for low insertion loss and high power handling capability millimeter-wave switch have been proposed and verified in accordance with the trend of 5G communication technology which is being commercialized recently. The proposed SPST switch consists of the 2-stacked shunt-arm (switch block) without the serial-arm. Measured results showed the low insertion loss performance of 1.76 dB and the power handling capability of bettern than 19.5 dBm in the switch ON-state at 94 GHz. Also, the proposed SPST switch has the high isolation performance of better than 30.75 dB and the improved power handling capability in switch OFF state by using the 4-branch shunt-arm with different FET-width.; In this dissertation, the following three subject were studied.

1. A programmable electronic impedance tuner available in practical PA robustness test.

2. Improved power handling capability RF switch design methodology based on CMOS SOI (Silicon-on-insulator) process, which has recently attracted attention as a RF switch device.

3. High-performance millimeter-wave switch over 94 GHz.

Recent rapid advances in mobile devices have increased demand for high-performance front-end modules (FEMs), including mobile power amplifiers (Pas), from mobile hardware manufacturers. The impedance tuner is a key equipment used for FEM development to find the input/output impedance matching conditions of the power amplifier according to the application (PA source/load-pull test) and to observe the FEM performance change by arbitrarily implementing the mismatched antenna conditions at the output stage of the fabricated FEM. And the hardware manufacturers’ demand for high performance impedance tuners is substantial. However, conventional mechanical impedance tuners used typically in industry increase the development time and cost of the PA due to slow operation speed, bulky size, and expensive equipment. To solve these problems, a programmable electronic impedance tuner having advantages of fast speed, small size and cost-effective has been proposed and its operation has been verified.

Various electronic impedance tuners have been reported as an alternative to conventional mechanical impedance tuners. However, these impedance tuners have a critical fault that makes it difficult to implement a uniform impedance distribution due to the limitations of the proposed circuit topology and the restricted ON/OFF-state characteristic (insertion loss/isolation) of the switch devices. Therefore, an electronic impedance tuner has been proposed that can implement uniform impedance distribution by using transission and reflection characteristics of a 3-dB 90 degree coupler. The proposed electronic impedance tuner was fabricated in three modules by using two main circuit topologies, and a PIN diode and a CMOS SOI FET-switch were used as switch devices. Various circuit technologies have been applied to ensure high SWR coverage while maintaining the advantage of high speed and small size. Ultimately, an electronic impedance tuner with a total of 24 phase variation in SWR = 2 to 6 and operating in the low-band (700 – 915 MHz) and mid-band (1.7 – 2.025 GHz) was fabricated. The fabricatd tuner showed very uniform reflection coefficient distribution with magnitude deviations of less than 0.001 / 0.006 at SWR = 2.5 / 6 and phase deviations of less than 5º. (PIN diode-type tuner, Ver.2). The proposed tuner can be used as a practical PA robustness test equipment because it can implement uniform impedance distribution. To verify the usefulness of the proposed tuner, a low-band PA robustness measurement under SWR = 6 was performed using the proposed PIN diode type impedance tuner(Ver.2). Measured results showed that the proposed tuner was in accord with the commercial mechanical tuner, showing gain deviations of less than 0.9 dB and ACLR deviations of less than 3 dB at SWR = 6 at Pin=20 dBm. The power handling capability of the PIN diode type impedance tuners(Ver.1 and 2) are limitated up to Pin = 20 dBm. However, an electronic impedance tuner using a CMOS SOI FET-switch (Ver.3) has a high power handling capability of 26 dBm.

Next, the study topic was naturally changed with the switch device which is the key component of the electronic impedance tuner. A circuit topology of the improved power handling capability RF switch based on CMOS SOI process which attracted attention as process for high performance RF switch has been proposed and verified. A 7-stacked SPST (Single-Pole Sing-Throw) switch with improved power handling capability compared to conventional 8-stacked SPST switches has been proposed. Measured results showed the insertion loss performance of 0.213 / 0.189 dB and the power handling capability of 38.6 / 38.5 dBm at 2 GHz in the conventional 8-staced switch and the proposed 7-stacked switch respectively. This is a result of the improved insertion loss about 11% without power handling capability degradation.

Lastly, the circuit topologies for low insertion loss and high power handling capability millimeter-wave switch have been proposed and verified in accordance with the trend of 5G communication technology which is being commercialized recently. The proposed SPST switch consists of the 2-stacked shunt-arm (switch block) without the serial-arm. Measured results showed the low insertion loss performance of 1.76 dB and the power handling capability of bettern than 19.5 dBm in the switch ON-state at 94 GHz. Also, the proposed SPST switch has the high isolation performance of better than 30.75 dB and the improved power handling capability in switch OFF state by using the 4-branch shunt-arm with different FET-width.