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Low-Temperature Processed High Performance Zinc-Oxynitride (ZnON) Thin-Film Transistor with Dual Gate Structure

Title
Low-Temperature Processed High Performance Zinc-Oxynitride (ZnON) Thin-Film Transistor with Dual Gate Structure
Author
박은재
Alternative Author(s)
박은재
Advisor(s)
박진성
Issue Date
2020-02
Publisher
한양대학교
Degree
Master
Abstract
Amorphous oxide semiconductors (AOSs) represented by a-InGaZnO (a-IGZO) have been commercialized in display industry because of their relative high mobility and uniformity. However, there is demand for higher mobility than that of a-IGZO semiconductor to develop next-generation display technologies including 8K ultra high definition (UHD) and over 240 Hz frame rate. In addition, the fact that a-IGZO semiconductor generally need relative high annealing temperature to activate electrical characteristics makes it difficult to apply to transparent flexible substrate such as polyethylene-2,6-naphthanlate (PEN) due to high thermal budget. In this research, high mobility, transparent and flexible Zinc oxynitrite (ZnON) based thin film transistors were fabricated with dual gate structure using low temperature process (< 150 oC) using UVO annealing method. The transfer characteristics were measured with three different types of gate bias sweep. In single gate driving mode (bottom gate sweep or top gate sweep), just one gate was swept from –20 V to 20 V, while other gate was kept ground. In dual gate driving mode, both bottom and top gate bias were swept with a same voltage value simultaneously. Dual gate driving, which makes that channel region is extended to bulk region, showed improved electrical performance such as saturation mobility (μsat) of 147 cm2/Vs and subthreshold swing (S.S) of 0.17 V/dec, compare to the single gate driving mode (μsat of 65.8 cm2/Vs and S.S of 0.43 V/dec for bottom gate sweep). The negative bias illumination stress (NBIS) stability was also improved as the value of threshold voltage shift decreased from -8.99 V (bottom gate sweep) and -9.54 V (top gate sweep) to -4.43 V (dual gate sweep) after the stress with gate bias of –10 V and illuminance of 1,000 lux for 3,600 sec due to the decrease in effect of interfacial trap sites and interface scattering. Transparent flexible ZnON based TFTs were also fabricated on PEN substrate, and it is confirmed that there is no difference of electrical performance after delamination from the carrier glass. The stability under mechanical stress was also enhanced in dual gate driving mode. Furthermore, dual gate structure was applied to ZnON phototransistor in order to investigate merits of dual gate structure as a phototransistor, and the reduction of persistent photoconductivity (PPC) phenomenon was observed in dual gate driving mode.
URI
https://repository.hanyang.ac.kr/handle/20.500.11754/123506http://hanyang.dcollection.net/common/orgView/200000436949
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > MATERIALS SCIENCE & ENGINEERING(신소재공학과) > Theses (Master)
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