A Low-Power 12-Bit Extended Counting ADC Without Calibration for CMOS Image Sensors

Abstract

This brief proposes a low-power 12-bit column-parallel extended counting analog-to-digital converter (EC ADC) without calibration for CMOS image sensors. The proposed 12-bit EC ADC uses the Delta Sigma ADC and single-slope ADC (SS ADC) to convert the input voltage to the upper 4 bit and lower 8 bit, respectively. It reduces power consumption by sharing a comparator between the Delta Sigma ADC and the SS ADC, and is robust to the inaccurate ramp signal. The 16-LSB linearity error of the ramp signal causes only 1 LSB linearity error of the proposed EC ADC. In addition, the proposed EC ADC improves the ADC linearity without calibration by adjusting the slope of the ramp signal in the lower 8-bit conversion phase according to the capacitance mismatch between the sampling and feedback capacitors. A test chip with 200 readout channels, each including the proposed EC ADC, was fabricated using an 0.18-mu m CMOS process. The measurement results show that the proposed EC ADC achieves a differential nonlinearity of +0.4/-0.3 LSB and an integral nonlinearity of +3.5/0 LSB without calibration. In addition, the measured signal-to-noise distortion ratio and effective number of bits are 65.4 dB and 10.5-bit, respectively. The measured power consumption per ADC is 22 mu W and the best figure of merit in power efficiency is achieved to be 82 fJ/step.