Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 송윤흡 | - |
dc.date.accessioned | 2019-12-03T05:17:05Z | - |
dc.date.available | 2019-12-03T05:17:05Z | - |
dc.date.issued | 2017-12 | - |
dc.identifier.citation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 17, no. 12, page. 9257-9261 | en_US |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.issn | 1533-4899 | - |
dc.identifier.uri | https://www.ingentaconnect.com/content/asp/jnn/2017/00000017/00000012/art00083 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/116826 | - |
dc.description.abstract | Using simulations, we investigated the impact of grain physical parameters in a poly-silicon channel on the dispersion of cell threshold voltages in a gate-all-around channel structure, which is used in 3-dimensional NAND flash memory. Here, cell characteristics were evaluated for various grain length (L-G) and grain boundary trap density (N-GB) values. The dispersion of the threshold voltages was investigated as a function of these parameters in a string with 12 cells. We confirmed that a shorter grain length and higher grain boundary trap density in a poly-silicon vertical channel resulted in poor cell characteristics, namely a lower cell current and a less favorable sub-threshold slope. In addition, we showed that the variations in cell characteristics in a string significantly increased with decreasing grain length and increased trap density in the poly-silicon channel. From these results, we expect that increasing the grain length and minimizing the grain boundary trap density are important methods of decreasing the dispersion of the cell threshold voltages in a string. | en_US |
dc.description.sponsorship | This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (NRF-2015R1A2A2A01007289). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | en_US |
dc.subject | 3D NAND Flash Memory | en_US |
dc.subject | Threshold Voltage Distribution | en_US |
dc.subject | Polysilicon Channel | en_US |
dc.subject | Grain | en_US |
dc.subject | Grain Boundary Trap | en_US |
dc.title | Impact of Grain Length and Grain Boundary on Dispersion of Threshold Voltage for 3-Dimensional Gate-All-Around Polysilicon Channel Memory | en_US |
dc.type | Article | en_US |
dc.relation.no | 12 | - |
dc.relation.volume | 17 | - |
dc.identifier.doi | 10.1166/jnn.2017.13902 | - |
dc.relation.page | 9257-9261 | - |
dc.relation.journal | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.contributor.googleauthor | Kim, Kyu-Beom | - |
dc.contributor.googleauthor | Oh, Young-Taek | - |
dc.contributor.googleauthor | Song, Yun-Heub | - |
dc.relation.code | 2017011537 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | yhsong2008 | - |
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