Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 최준원 | - |
dc.date.accessioned | 2019-12-02T05:55:00Z | - |
dc.date.available | 2019-12-02T05:55:00Z | - |
dc.date.issued | 2017-11 | - |
dc.identifier.citation | CIRCUITS SYSTEMS AND SIGNAL PROCESSING, v. 36, no. 11, page. 4309-4325 | en_US |
dc.identifier.issn | 0278-081X | - |
dc.identifier.issn | 1531-5878 | - |
dc.identifier.uri | https://link.springer.com/article/10.1007%2Fs00034-017-0534-5 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/116337 | - |
dc.description.abstract | Many of the existing supply voltage overscaling (VOS) techniques allow an increase in the critical path delay, resulting in the reduction in the throughput rate. On the contrary, the VOS techniques without affecting on the throughput rate induce loss of the system performance by timing errors. In this paper, we propose a perfect timing error cancelation (PTEC) system which not only retains the throughput rate, but also perfectly recovers the system performance. In the arithmetic units whose output bits are sequentially computed, it is observed that timing violations due to VOS occur at some designated highest order output bits, resulting in the large error on the output value. By exploiting this property, a novel timing error cancelation technique is presented by modeling the timing error signal and deriving the condition for the perfect recovery from the impaired signal. The proposed PTEC system is verified with the design example of a 1616 unsigned carry-save multiplier. From simulation results, it is found that the proposed PTEC system with 200 mV overscaling offers 38% power reduction with maintaining the throughput rate as well as the system functionality compared to the conventional design with the nominal supply voltage (=1 V). | en_US |
dc.description.sponsorship | This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2014R1A1A2055805), the ICT program of MSIP/IITP, Republic of Korea [B0101-16-1347], and the National Research Foundation (NRF) of Korea (Grant NRF-2015M1A3A3A02010753). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | SPRINGER BIRKHAUSER | en_US |
dc.subject | Voltage overscaling | en_US |
dc.subject | Timing error recovery | en_US |
dc.subject | Low-power arithmetic unit | en_US |
dc.subject | Carry-save multiplier | en_US |
dc.subject | Algorithmic noise tolerance | en_US |
dc.title | Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation | en_US |
dc.type | Article | en_US |
dc.relation.no | 11 | - |
dc.relation.volume | 36 | - |
dc.identifier.doi | 10.1007/s00034-017-0534-5 | - |
dc.relation.page | 4309-4325 | - |
dc.relation.journal | CIRCUITS SYSTEMS AND SIGNAL PROCESSING | - |
dc.contributor.googleauthor | Chang, Ik Joon | - |
dc.contributor.googleauthor | Park, Sang Yoon | - |
dc.contributor.googleauthor | Choi, Jun Won | - |
dc.relation.code | 2017006838 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DIVISION OF ELECTRICAL AND BIOMEDICAL ENGINEERING | - |
dc.identifier.pid | junwchoi | - |
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