Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김태환 | - |
dc.date.accessioned | 2019-11-26T05:29:34Z | - |
dc.date.available | 2019-11-26T05:29:34Z | - |
dc.date.issued | 2017-06 | - |
dc.identifier.citation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 17, no. 6, page. 4145-4148 | en_US |
dc.identifier.isbn | 10.1166/jnn.2017.13411 | - |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.issn | 1533-4899 | - |
dc.identifier.uri | https://www.ingentaconnect.com/content/asp/jnn/2017/00000017/00000006/art00080 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/114593 | - |
dc.description.abstract | The effect of the nanoscale bitline string thickness on the electrical characteristics of vertical NAND flash memory devices was investigated. The trapped charge magnitude in the nitride layer increased with increasing a string thickness up to 20 nm. The program characteristics of vertical NAND flash memory devices with various thicknesses of bitline strings were attributed to the distribution of the trap charges in the nitride trap layers. The cell-to-cell interference in vertical NAND flash memory devices with a cell-to-cell distance of 40 nm was not significantly affected by variation in the string thickness. The threshold voltage shift of an optimal memory device with a string thickness of 20 nm was 0.69 V, which was the largest value among the simulated data. | en_US |
dc.description.sponsorship | This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2016R1A2A1A05005502), and this research was partially supported by Samsung Electronics Co. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | en_US |
dc.subject | Vertical NAND Flash Memories | en_US |
dc.subject | Trap Charge Layer | en_US |
dc.subject | String Thickness | en_US |
dc.subject | Threshold Voltage | en_US |
dc.title | Effect of the Nanoscale Bitline String Thickness on the Electric Characteristics of Vertical NAND Flash Memory Devices | en_US |
dc.type | Article | en_US |
dc.relation.no | 6 | - |
dc.relation.volume | 17 | - |
dc.relation.page | 4145-4148 | - |
dc.relation.journal | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.contributor.googleauthor | Jung, Hyun Soo | - |
dc.contributor.googleauthor | Ahn, Joonsung | - |
dc.contributor.googleauthor | Kim, Tae Whan | - |
dc.relation.code | 2017011537 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | twk | - |
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