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dc.contributor.author김태환-
dc.date.accessioned2019-11-26T05:29:34Z-
dc.date.available2019-11-26T05:29:34Z-
dc.date.issued2017-06-
dc.identifier.citationJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 17, no. 6, page. 4145-4148en_US
dc.identifier.isbn10.1166/jnn.2017.13411-
dc.identifier.issn1533-4880-
dc.identifier.issn1533-4899-
dc.identifier.urihttps://www.ingentaconnect.com/content/asp/jnn/2017/00000017/00000006/art00080-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/114593-
dc.description.abstractThe effect of the nanoscale bitline string thickness on the electrical characteristics of vertical NAND flash memory devices was investigated. The trapped charge magnitude in the nitride layer increased with increasing a string thickness up to 20 nm. The program characteristics of vertical NAND flash memory devices with various thicknesses of bitline strings were attributed to the distribution of the trap charges in the nitride trap layers. The cell-to-cell interference in vertical NAND flash memory devices with a cell-to-cell distance of 40 nm was not significantly affected by variation in the string thickness. The threshold voltage shift of an optimal memory device with a string thickness of 20 nm was 0.69 V, which was the largest value among the simulated data.en_US
dc.description.sponsorshipThis research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2016R1A2A1A05005502), and this research was partially supported by Samsung Electronics Co.en_US
dc.language.isoen_USen_US
dc.publisherAMER SCIENTIFIC PUBLISHERSen_US
dc.subjectVertical NAND Flash Memoriesen_US
dc.subjectTrap Charge Layeren_US
dc.subjectString Thicknessen_US
dc.subjectThreshold Voltageen_US
dc.titleEffect of the Nanoscale Bitline String Thickness on the Electric Characteristics of Vertical NAND Flash Memory Devicesen_US
dc.typeArticleen_US
dc.relation.no6-
dc.relation.volume17-
dc.relation.page4145-4148-
dc.relation.journalJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY-
dc.contributor.googleauthorJung, Hyun Soo-
dc.contributor.googleauthorAhn, Joonsung-
dc.contributor.googleauthorKim, Tae Whan-
dc.relation.code2017011537-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidtwk-
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COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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