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dc.contributor.author신현철-
dc.date.accessioned2019-09-20T02:18:42Z-
dc.date.available2019-09-20T02:18:42Z-
dc.date.issued2005-05-
dc.identifier.citation2005년도 SOC 학술대회, Page. 85 - 89en_US
dc.identifier.urihttp://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01731639&language=ko_KR-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/110531-
dc.description.abstractRecently, mobile information terminals such as cellular phones and personal digital assistants(PDAs) are becoming more popular, and their market is growing rapidly. As well as H.264 image processing, we expect that even three-dimensional (3-D) graphics processing, which generally needs large hardware and extremely high computational power, will be necessary for many mobile communication applications. Furthermore, low power and small area are also important issues in IC design. In this paper, we propose a low power and small area multimedia processor for future mobile applications. Various multimedia functions including H.264 motion compensation and 3-D graphics span processing are implemented by combining dedicated hardware accelerators and a general-purpose processor. The designed hardware shows satisfactory results in performance and area.-
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.titleReconfigurable Architecture Design for H.264 Motion Compensation and 3D Graphics Span Processingen_US
dc.typeArticleen_US
dc.contributor.googleauthor박정애-
dc.contributor.googleauthor윤미선-
dc.contributor.googleauthor신현철-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidshin-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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