PREDICTION OF TIMES-TO-FAILURE OF SEMICONDUCTOR CHIPS USING VMIN DATA

Abstract

Accelerated Life Testing (ALT) aims at predicting times-to-failure under normal operating condition. The prediction requires times-to-failure data under ALT operation conditions, however, it is difficult to obtain the times-to-failure data of semiconductor chips when only few failures occur. In this regard, we attempt to predict times-to-failure of semiconductor chips by using Vmin data. Since Vmin are measured for all of tested chips regardless of failure, we can predict times-to-failure for all of the chips. The proposed method is more informative and robust than the traditional life data approach in that all of the tested semiconductor chips participate in the life prediction process.