Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 어영선 | - |
dc.date.accessioned | 2019-07-24T04:58:25Z | - |
dc.date.available | 2019-07-24T04:58:25Z | - |
dc.date.issued | 2006-03 | - |
dc.identifier.citation | 7th International Symposium on Quality Electronic Design (ISQED'06), Page. 419-424 | en_US |
dc.identifier.issn | 1948-3287 | - |
dc.identifier.issn | 1948-3295 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/abstract/document/1613173 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/107766 | - |
dc.description.abstract | A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using traveling-wave-based waveform approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.title | Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/ISQED.2006.57 | - |
dc.contributor.googleauthor | Je, Taeyong | - |
dc.contributor.googleauthor | Eo, Yungseon | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | eo | - |
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