PREDICTION OF TIMES-TO-FAILURE OF SEMICONDUCTOR CHIPS USING VMIN DATA
- Title
- PREDICTION OF TIMES-TO-FAILURE OF SEMICONDUCTOR CHIPS USING VMIN DATA
- Author
- 이희정
- Keywords
- accelerated life testing; times-to-failure; semiconductor
- Issue Date
- 2019-03
- Publisher
- UNIV CINCINNATI INDUSTRIAL ENGINEERING
- Citation
- INTERNATIONAL JOURNAL OF INDUSTRIAL ENGINEERING-THEORY APPLICATIONS AND PRACTICE, v. 26, Issue 1, Page. 83-91
- Abstract
- Accelerated Life Testing (ALT) aims at predicting times-to-failure under normal operating condition. The prediction requires
times-to-failure data under ALT operation conditions, however, it is difficult to obtain the times-to-failure data of
semiconductor chips when only few failures occur. In this regard, we attempt to predict times-to-failure of semiconductor
chips by using Vmin data. Since Vmin are measured for all of tested chips regardless of failure, we can predict times-to-failure for all of the chips. The proposed method is more informative and robust than the traditional life data approach in that all of the tested semiconductor chips participate in the life prediction process.
- URI
- http://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=a9h&AN=135984085https://repository.hanyang.ac.kr/handle/20.500.11754/106978
- ISSN
- 1072-4761; 1943-670X
- Appears in Collections:
- ETC[S] > 연구정보
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