A Design-for-Debug(DfD) for NoC-Based SoC Debugging via NoC
- Title
- A Design-for-Debug(DfD) for NoC-Based SoC Debugging via NoC
- Author
- 박성주
- Keywords
- design-for-debug (DfD); system-on-chip (SoC); network-on-chip (NoC); PSMI
- Issue Date
- 2008-11
- Publisher
- IEEE
- Citation
- 2008 17th Asian Test Symposium, Article no. 4711607, Page. 289-294
- Abstract
- This paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core debug supporting logics which can support transaction-based debug. A debug interface unit is also presented to enable debug data transfer through an NoC between an external debugger and a coreunder-debug (CUD). The proposed approach supports debug of designs with multiple clock domains. It also supports collection of trace signatures to facilitate debug of long pattern sequences. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead. We also present simulation result to verify proper operation of the debug components.
- URI
- https://ieeexplore.ieee.org/abstract/document/4711607https://repository.hanyang.ac.kr/handle/20.500.11754/105030
- ISBN
- 978-0-7695-3396-4
- ISSN
- 1081-7735
- DOI
- 10.1109/ATS.2008.15
- Appears in Collections:
- COLLEGE OF COMPUTING[E](소프트웨어융합대학) > COMPUTER SCIENCE(소프트웨어학부) > Articles
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