Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 신현철 | - |
dc.date.accessioned | 2019-05-20T02:26:26Z | - |
dc.date.available | 2019-05-20T02:26:26Z | - |
dc.date.issued | 2008-06 | - |
dc.identifier.citation | 대한전자공학회 2008년 하계종합학술대회, Page. 453-454 | en_US |
dc.identifier.uri | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE01017094 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/104649 | - |
dc.description.abstract | Modern VLSI designs get increasingly complex and time-to-market constraints get tighter. Using high level languages is one of the most promising solutions for improving design productivity by raising the level of abstraction. In high level synthesis process, most important step is scheduling. In this paper, we propose fast and efficient scheduling method under timing constraint based on list scheduling. Experimental results on well known data path intensive designs show fast execution times (less than 0.5 sec) and similar results when compared to optimal solutions [1]. | en_US |
dc.language.iso | ko_KR | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.title | 시간 제약 조건하에서 상위 수준 합성을 위한 효율적인 스케줄링 기법 | en_US |
dc.title.alternative | An Efficient Scheduling Technique for High Level Synthesis under Timing Constraints | en_US |
dc.type | Article | en_US |
dc.contributor.googleauthor | 김지웅 | - |
dc.contributor.googleauthor | 정우성 | - |
dc.contributor.googleauthor | 신현철 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | shin | - |
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