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dc.contributor.author어영선-
dc.date.accessioned2019-05-13T07:31:13Z-
dc.date.available2019-05-13T07:31:13Z-
dc.date.issued2009-07-
dc.identifier.citation대한전자공학회 2009년 하계종합학술대회, Page. 407-408en_US
dc.identifier.urihttp://www.dbpia.co.kr/Journal/ArticleDetail/NODE02335943-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/104049-
dc.description.abstractA via is experimentally characterized by using high-frequency s-parameter measurements. Test patterns are designed and fabricated by using a package process. They are measured by using VNA (vector network analyzer) up to 25GHz. The parasitic effects due to access lines for on-wafer probing are deembedded. Then modeling the via as T-type circuit, the circuit model parameters are determined. It is shown that the proposed technique has excellent agreement with the measured s-parameters.en_US
dc.description.sponsorship본 논문은 2009년도 정부(교육과학기술부)의 재원으 로 한국과학재단의 지원을 받아 수행된 연구임 (No. 2009-0075375).en_US
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.title다층 배선 비아(Via)의 고주파 측정 기반 회로 모델링en_US
dc.title.alternativeCircuit Modeling of Multi-Layer Interconnect Via based on High Frequency Measurementen_US
dc.typeArticleen_US
dc.contributor.googleauthor김혜원-
dc.contributor.googleauthor김동철-
dc.contributor.googleauthor어영선-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pideo-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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