Cycle Accurate Memory Delay Modeling for Off-Chip DRAMs

Abstract

MPSoCs are gaining popularity because of its potential to solve computationally expensive problems. MPSoCs frequently use two kinds of memories; on-chip SRAMs and off-chip DRAMs. Processors in multicore systems usually take many clock cycles for the transfer of data to/from off-chip memories which affects the overall system performance. While an on-chip memory operation takes one or two clock cycles, an off-chip memory access takes significantly more number of clock cycles. Therefore, delay modeling for off-chip memories is important to optimize the overall system performance. This paper proposes the cycle accurate delay modeling techniques for finding the exact delays for off-chip memories.