Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 신현철 | - |
dc.date.accessioned | 2019-05-13T04:22:11Z | - |
dc.date.available | 2019-05-13T04:22:11Z | - |
dc.date.issued | 2009-05 | - |
dc.identifier.citation | 대한전자공학회 2009년 SoC학술대회, Page. 255-258 | en_US |
dc.identifier.uri | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE01229245 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/103949 | - |
dc.description.abstract | MPSoCs are gaining popularity because of its potential to solve computationally expensive problems. MPSoCs frequently use two kinds of memories; on-chip SRAMs and off-chip DRAMs. Processors in multicore systems usually take many clock cycles for the transfer of data to/from off-chip memories which affects the overall system performance. While an on-chip memory operation takes one or two clock cycles, an off-chip memory access takes significantly more number of clock cycles. Therefore, delay modeling for off-chip memories is important to optimize the overall system performance. This paper proposes the cycle accurate delay modeling techniques for finding the exact delays for off-chip memories. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.subject | memory delay modeling | en_US |
dc.subject | memory optimization | en_US |
dc.title | Cycle Accurate Memory Delay Modeling for Off-Chip DRAMs | en_US |
dc.type | Article | en_US |
dc.contributor.googleauthor | Khan, Sultan Daud | - |
dc.contributor.googleauthor | Shin, Hyunchul | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | shin | - |
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