Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 권오경 | - |
dc.date.accessioned | 2019-02-20T07:49:55Z | - |
dc.date.available | 2019-02-20T07:49:55Z | - |
dc.date.issued | 2016-10 | - |
dc.identifier.citation | 2016 International SoC Design Conference (ISOCC), Page. 262-263 | en_US |
dc.identifier.isbn | 978-1-5090-3219-8 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/7799775?arnumber=7799775&SID=EBSCO:edseee | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/99137 | - |
dc.description.abstract | This paper proposes a low power 10-bit single-slope analog-to-digital converter (SS-ADC) for CMOS image sensors (CISs) with a column-parallel readout structure. The power consumption of the proposed SS-ADC is reduced by using a power gating scheme for the comparator and multi-clocks having different frequencies. The proposed SS-ADC was designed using a 0.13μm CIS process technology. The simulation results show that the power consumption of the proposed SS-ADC is 9.7 μW, which is 59.4 % less than that of the conventional SS-ADC. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.subject | single-slope ADC | en_US |
dc.subject | CMOS image sensor | en_US |
dc.subject | counter | en_US |
dc.subject | comparator | en_US |
dc.subject | shot noise | en_US |
dc.title | A Low-Power 10-bit Single-Slope ADC Using Power Gating and Multi-Clocks for CMOS Image Sensors | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/ISOCC.2016.7799775 | - |
dc.relation.page | 262-263 | - |
dc.contributor.googleauthor | Jeon, Byoung-Kwan | - |
dc.contributor.googleauthor | Hong, Seong-Kwan | - |
dc.contributor.googleauthor | Kwon, Oh-Kyong | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | okwon | - |
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