Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bharanitharan, Karunanithi | - |
dc.date.accessioned | 2018-05-23T05:36:33Z | - |
dc.date.available | 2018-05-23T05:36:33Z | - |
dc.date.issued | 2016-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v. 24, NO 5, Page. 1993-1997 | en_US |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.issn | 1557-9999 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/7293215/ | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/71474 | - |
dc.description.abstract | This brief presents a fixed-point architecture based on a reconfigurable scheme for integrating several commonly used mathematical operations of speech signal processing. The proposed design can perform two transcendental mathematical operations called logarithm and powering, and three commonly used computations with similar operations named polynomial calculation, filtering, and windowing. By analyzing the adopted algorithms of the above five operations, a simplified computing unit is designed. This unit can combine six types of operations by reconfiguring the data paths, and the same multiply-add architecture can be reused for reducing the redundant usage of logic gates. The experimental results reveal that the proposed design can work at a 200-MHz clock rate, and its gate count only has 11.9k. Compared with the results of the floating-point function, the median errors of the proposed design for computing the powering and logarithmic functions are 0.57% and 0.11%, respectively. Such results indicate that this simple architecture can be effectively used in most speech processing applications. | en_US |
dc.description.sponsorship | This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 104-2221-E-366-001. The work of K. Bharanitharan was supported by Hanyang University under Research Fund HY-2015. (Corresponding author: K. Bharanitharan.) | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Fixed-point system | en_US |
dc.subject | iterative design | en_US |
dc.subject | speech processing | en_US |
dc.title | Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing | en_US |
dc.type | Article | en_US |
dc.relation.no | 5 | - |
dc.relation.volume | 24 | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2477312 | - |
dc.relation.page | 1993-1997 | - |
dc.relation.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.contributor.googleauthor | Chang, Chung-Hsien | - |
dc.contributor.googleauthor | Chen, Shi-Huang | - |
dc.contributor.googleauthor | Chen, Bo-Wei | - |
dc.contributor.googleauthor | Ji, Wen | - |
dc.contributor.googleauthor | Bharanitharan, K. | - |
dc.contributor.googleauthor | Wang, Jhing-Fa | - |
dc.relation.code | 2016006630 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | darrenk | - |
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