3차원 V-NAND 플래시 메모리 구조의 신뢰성에 기계적 응력이 미치는 영향성에 대한 시뮬레이션 연구

Abstract

The memory market has been growing steadily due to the rapid spread of mobile devices such as smartphones and tablet devices, in addition to the increasing demand for data centers capable of analyzing big data and supporting artificial intelligence, which are core technologies in the fourth industrial revolution. As a result, demand for data storage devices has expanded rapidly, and NAND flash is the most common non-volatile memory used for mass storage. Since Toshiba developed the world’s first 4 Mb NAND-type EEPROM in 1991, manufacturers have continued to strive to increase the density and to lower the fabrication cost. For conventional planar NAND flash memories, an approach to reduce the cell size in the horizontal direction was used to improve the density; however, this scaling method is strongly dependent on the lithography technology. Below the 20 nm technology node, scaling has slowed due to physical and electrical challenges. The physical limitation is expected to reach below 1Z nm technology because cell-to-cell interference becomes more intense as the distance between cells decreases. In addition, multiple patterning techniques and multilevel devices have been adopted to lower the fabrication cost; however, these techniques have issues of degradation in performance and reliability. In order to overcome the scaling challenges of the conventional planar NAND flash memory, 3D architecture was proposed in which the memory cells are stacked vertically. This innovative structure enables higher integration of the memory chip within the same area by stacking more cells vertically, as well as the improvement of the cell performance and reliability over 2D NAND. For this reason, most manufacturers have been mass-producing higher density products with this inherent architecture. Because of the complexity of the 3D NAND structure, as the number of vertically stacked cells increases, the degradation in performance and reliability intensifies due to the variation in cell characteristics with different cell locations, and the deformation caused by mechanical stress during the manufacturing process. In particular, structural deformation and wafer warpage have a great influence on the overall yield, thus prediction and analysis using process simulation are necessary. Advanced technologies for unit processes with uniform and low stress are also crucial. In this thesis, the stress that may occur during the manufacturing processes for 3D V-NAND architecture was implemented using process simulation. The effects of residual stress on the V-NAND structure and substrate warpage according to 1) the process sequence, 2) CD variation, and 3) an increase in stacked layers were confirmed. The simulation results showed that the intrinsic stress of the tungsten slit is dominant and the residual stress in the inner tungsten WL layers with large CTE has a significant influence. The stress affects the lateral directions of the silicon substrate, which may lead the substrate to warp. In addition, the complex stress relaxation after structural and temperature changes causes non-uniformity between the memory cells, which causes reliability degradation in the memory device. These phenomena intensify as the number of stacked WL layers in 3D NAND flash memory increases, and therefore, process technologies that can suppress the stress are essential.