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A 1.92-Megapixel CMOS Image Sensor With Column-Parallel Low-Power and Area-Efficient SA-ADCs

Title
A 1.92-Megapixel CMOS Image Sensor With Column-Parallel Low-Power and Area-Efficient SA-ADCs
Author
권오경
Keywords
CMOS image sensor; column-parallel readout architecture; low-power consumption; small-area successive approximation analog-to-digital converter (SA-ADC)
Issue Date
2012-06
Publisher
IEEE
Citation
IEEE Transactions on Electron Devices, 2012 59(6), P.1693-1700
Abstract
This paper presents a CMOS image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is 9 mu\m x 425 mu m. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-mu m CMOS process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively.
URI
https://ieeexplore.ieee.org/document/6178785/http://hdl.handle.net/20.500.11754/67990
ISSN
0018-9383
DOI
10.1109/TED.2012.2190936
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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