Investigation of Vertical Channel Architecture for Bulk Erase Operation in Three-Dimensional NAND Flash Memory
- Title
- Investigation of Vertical Channel Architecture for Bulk Erase Operation in Three-Dimensional NAND Flash Memory
- Author
- 송윤흡
- Keywords
- DIFFUSION; INDIUM; INDIUM
- Issue Date
- 2012-10
- Publisher
- JAPAN SOCIETY OF APPLIED PHYSICS
- Citation
- Japanese Journal of Applied Physics, November 2012, 51(11), pp.116501
- Abstract
- A bit-cost scalable (BiCS) technology using a bulk erasing method instead of the conventional erase operation using gate-induced drain leakage (GIDL) is proposed to realize better cell characteristics and process feasibility for three-dimensional (3D) NAND flash memory. This has an additional electrode layer for a bulk erase operation in the middle of a vertical string cell. Here, we confirmed that this structure using an additional electrode provides good program and erasing speed by simulation. Furthermore, junction engineering is performed to realize a polysilicon layer of the flat plate type as a bulk electrode for better design feasibility. From this result, we expect that a bulk erasable BiCS technology using a flat plate erase electrode can be a candidate 3D NAND flash memory technology. (C) 2012 The Japan Society of Applied Physics
- URI
- http://iopscience.iop.org/article/10.1143/JJAP.51.116501/metahttp://hdl.handle.net/20.500.11754/67332
- ISSN
- 0021-4922
- DOI
- 10.1143/JJAP.51.116501; 10.1143/JJAP.51.116501
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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