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A ΔΣ-cyclic Hybrid ADC for Parallel Readout Sensor Applications

Title
A ΔΣ-cyclic Hybrid ADC for Parallel Readout Sensor Applications
Author
권오경
Keywords
Components, Circuits, Devices and Systems; Computing and Processing; Bioengineering; Communication, Networking and Broadcast Technologies; Capacitors; Operational amplifiers; Capacitance; Power demand; Signal to noise ratio; Switches
Issue Date
2012-05
Publisher
IEEE
Citation
International Symposium on Circuits and Systems Circuits and Systems, May 2012, P.532-535
Abstract
In this paper, an ADC for parallel readout to convert large amount data in sensor applications is proposed. The ADC achieves small area and low power consumption by using two-step conversion. A 1 st -order ΔΣ ADC converts coarse bits and then a cyclic ADC converts fine bits. An operational amplifier, comparators, capacitors, and switches used in the ADCs are efficiently shared to reduce power consumption and area. The proposed ADC has simple switching sequence, large tolerance to comparator offset and shared reference voltage between the coarse and fine ADCs. The designed circuit was fabricated in 0.18 μm CMOS using a 1.8 V supply voltage. It consumes 24 μW with 5 MHz clock speed. The measurement results show that SNR is varied from 47.89 to 57.58 dB according to the number of oversampling at 1 st -order ΔΣ ADC.
URI
http://ieeexplore.ieee.org/document/6272084/http://hdl.handle.net/20.500.11754/49909
ISBN
978-1-4673-0218-0; 978-1-4673-0217-3; 978-1-4673-0219-7
ISSN
0271-4302
DOI
10.1109/ISCAS.2012.6272084
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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