Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology
- Title
- Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology
- Author
- 백상현
- Keywords
- Clock jitter; clock mesh; clock race; radiation hardening; single event effect; soft error
- Issue Date
- 2016-02
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Citation
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v. 63, No. 1, Page. 385-391
- Abstract
- Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers.
- URI
- http://ieeexplore.ieee.org/abstract/document/7407517/http://hdl.handle.net/20.500.11754/49658
- ISSN
- 0018-9499; 1558-1578
- DOI
- 10.1109/TNS.2015.2509443
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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