Leakage-aware adaptive routing for pipelined on-chip networks in ultra-deep sub-micron technologies
- Title
- Leakage-aware adaptive routing for pipelined on-chip networks in ultra-deep sub-micron technologies
- Author
- 송용호
- Keywords
- leakage power; power-gating; on-chip network; adaptive routing
- Issue Date
- 2012-12
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Citation
- IEICE ELECTRONICS EXPRESS, 2012, 9(24), P.1887-1892
- Abstract
- As semiconductor process technology continues to scale down to the ultra-deep sub-micron level, leakage power becomes a critical design constraint for on-chip networks (OCNs). Power gating is widely used to reduce the OCN leakage power; however, it does not work well with adaptive routing owing to its aggressive use of free links and router buffers to achieve high performance. In this paper, a novel leakage-aware adaptive routing algorithm to increase the power-gating effect by routing packets with minimal link activation is proposed. Experimental results show that the proposed algorithm effectively achieves a reduction in the overall network leakage power of up to 11.6% greater than the conventional adaptive routing algorithm, with a little sacrificing network bandwidth.
- URI
- https://www.jstage.jst.go.jp/article/elex/9/24/9_1887/_articlehttp://hdl.handle.net/20.500.11754/48358
- ISSN
- 1349-2543
- DOI
- 10.1587/elex.9.1887
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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