In-Page Error Correction Code Management for MLC Flash Storages

Abstract

Memory manufacturers have recently advanced silicon technology to implement the multi-level cell technique onto NAND flash for the reduction of per-bit device cost. However, this technical improvement has introduced an additional problem of reliability and/or durability degradation, leading to the inevitable use of error detection and correction techniques. To increase the number of correctable error bit in recent flash memories, ECC techniques tend to use longer code bits. As the silicon technology of NAND device evolves, such growing code bits for a user data page could overflow its corresponding spare area in later devices. In this paper, we propose a novel management mechanism of excessively long error correction codes using user data area. The proposed mechanism is capable of providing error correction capability for highly error-prone NAND devices by efficiently managing long ECC codes only with negligible performance degradation.