Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer
- Title
- Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer
- Other Titles
- HfAlO Tunnel Layer
- Author
- 김은규
- Issue Date
- 2012-06
- Publisher
- IOP PUBLISHING LTD, TEMPLE CIRCUS, TEMPLE WAY, BRISTOL BS1 6BE, ENGLAND
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS, 51, 6, 06FE13
- Abstract
- WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at +/- 7 V were 300 mu s and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application. (C) 2012 The Japan Society of Applied Physics
- URI
- http://iopscience.iop.org/article/10.1143/JJAP.51.06FE13/metahttp://hdl.handle.net/20.500.11754/40171
- ISSN
- 0021-4922
- DOI
- 10.1143/JJAP.51.06FE13
- Appears in Collections:
- COLLEGE OF NATURAL SCIENCES[S](자연과학대학) > PHYSICS(물리학과) > Articles
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