A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process

Title
A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process
Authors
유창식
Keywords
I; O circuit; voltage stress; bidirectional I; O; CMOS
Issue Date
2015-06
Publisher
WILEY-BLACKWELL
Citation
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, v. 43, NO 6, Page. 822-828
Abstract
A 5.25-V-tolerant bidirectional I/O circuit has been developed in a 28-nm standard complementary metal-oxide-semiconductor (CMOS) process with only 0.9 and 1.8V transistors. The transistors of the I/O circuit are protected from over-voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n-well bias level of the p-type metal-oxide-semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25-V-tolerant bidirectional I/O circuit occupies 40 mu mx170 mu m of silicon area. Copyright (c) 2014 John Wiley Sons, Ltd.
URI
http://onlinelibrary.wiley.com/doi/10.1002/cta.1981/fullhttp://hdl.handle.net/20.500.11754/25838
ISSN
0098-9886; 1097-007X
DOI
http://dx.doi.org/10.1002/cta.1981
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > DEPARTMENT OF ELECTRONIC ENGINEERING(융합전자공학부) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE