Heterogeneous 3D Sequential CFET with Ge (110) Nanosheet p-FET on Si (100) bulk n-FET by Direct Wafer Bonding

Abstract

In this work, we demonstrated 3D sequential complementary field-effect-transistor (CFET) by direct wafer bonding (DWB) technique and a low-temperature process for monolithic 3D (M3D) integration using a high-performance top Ge (110)/<110> channel on bottom Si CMOS. Here, the maximum thermal budget was up to 400 °C during the fabrication of top Ge FET, allowing high-performance heterogenous Ge/Si CFET without damage to bottom Si FETs. Furthermore, we systematically investigated the mobility enhancement to channel orientation in thin Ge (110) nanosheet channel pFET. Low effective hole mass along <110> direction on Ge (110), which was calculated by the k·p method, provided record high mobility of approximately 400 cm2 /V∙s (corresponds to 743 cm2 /V∙s when normalized by footprint) among the reported Ge pFET with similar channel thicknesses at room temperature.