Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 장태환 | - |
dc.date.accessioned | 2023-12-21T07:53:12Z | - |
dc.date.available | 2023-12-21T07:53:12Z | - |
dc.date.issued | 2023-10 | - |
dc.identifier.citation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 31, NO. 10, Page. 1.0-5.0 | - |
dc.identifier.issn | 1063-8210;1557-9999 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/10190110 | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/187683 | - |
dc.description.abstract | In this study, we present a low-phase-noise 20-GHz phase locked loop (PLL) with simultaneous gm-boosted and third-harmonic impedance-tuned voltage-controlled oscillator (VCO). The proposed PLL is implemented using the 65-nm CMOS technology. By both implementing a cross-coupled center-tapped inductor and controlling the harmonic impedance, the phase noise is improved by approximately 3.4 dB. An auxiliary cross-coupled pair (CCP) is used to boost the transconductance, while a parallel quarter-wave open stub is added to minimize the second-harmonic impedance for the output signal as the squared waveform. The proposed PLL demonstrated a measured phase noise of - 102.05 dBc/Hz at a 1-MHz offset frequency. Based on the measured phase noise, the proposed PLL can achieve a figure of merit (FOM) of - 174.35 dBc/Hz, while it consumes 23.6 mW with a supply voltage of 1 V. | - |
dc.description.sponsorship | This work was supported in part by the National Research Foundation of Korea (NRF) funded by the South Korean government (Ministry of Science, ICT and Future Planning, MSIP) under Grant 2022R1F1A1072517 and in part by the Institute of Information & amp; Communications Technology Planning & amp; Evaluation (IITP), High Resolution Vector Network Analyzer SW Development supporting Sub-THz Frequency Band Grant through the Korean Government (MSIT) under Grant 2022-0-00859.& nbsp; | - |
dc.language | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.subject | 20 GHz | - |
dc.subject | CMOS | - |
dc.subject | frequency synthesizer | - |
dc.subject | LC oscillator | - |
dc.subject | low phase noise | - |
dc.subject | low power | - |
dc.subject | phase-locked loop (PLL) | - |
dc.subject | voltage-controlled oscillator (VCO) | - |
dc.title | Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g(m) -Boosting Technique | - |
dc.type | Article | - |
dc.relation.no | 10 | - |
dc.relation.volume | 31 | - |
dc.identifier.doi | 10.1109/TVLSI.2023.3294404 | - |
dc.relation.page | 1.0-5.0 | - |
dc.relation.journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | - |
dc.contributor.googleauthor | Lee, Hee Sung | - |
dc.contributor.googleauthor | Jang, Tae Hwan | - |
dc.contributor.googleauthor | Kim, Joon Hyung | - |
dc.contributor.googleauthor | Park, Chul Soon | - |
dc.sector.campus | E | - |
dc.sector.daehak | 공학대학 | - |
dc.sector.department | 전자공학부 | - |
dc.identifier.pid | hundredwin | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.