Performance Improvement by Logic Sharing on Using Unused Spare Columns for Memory EC

Abstract

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories for the purpose of allowing for repair in the presence of defective cells or bit lines. In many cases, the repair process will not use all spare columns. Schemes are proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in SEC-DED. These additional check bits increase the dimensions of the H-matrix. The increased number of 1s in the H-matrix increases not only the area overhead but also the delay of the whole system. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area over head and delay.