Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유봉영 | - |
dc.date.accessioned | 2023-05-19T05:48:12Z | - |
dc.date.available | 2023-05-19T05:48:12Z | - |
dc.date.issued | 2022-03 | - |
dc.identifier.citation | ECS Journal of Solid State Science and Technology, v. 11, NO. 3, article no. 034001, Page. 1-8 | - |
dc.identifier.issn | 2162-8769;2162-8777 | - |
dc.identifier.uri | https://iopscience.iop.org/article/10.1149/2162-8777/ac56c0 | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/180925 | - |
dc.description.abstract | Cu electrochemical polishing for planarization in the redistribution layer (RDL) process and the effects of Cu overburden profiles on Cu electrochemical polishing were investigated. Despite the fact that Cu electrochemical polishing is a feasible alternate planarization method, there are issues with obtaining void and bump-free overburden profiles associated with overpolishing for wide trenches. To ensure uniform electrochemical polishing for all width patterns, Cu overburdens were tuned by changing leveler additive concentration, resulting in bumps on the trenches. Uniform Cu overburden polishing was observed at similar overburden areas for all width patterns. The Cu electrochemical polishing results indicated that overburden on trenches and on interlayer dielectrics were important for uniform Cu overburden electrochemical polishing. | - |
dc.description.sponsorship | This research was supported by the Technology Innovation Program (20017379, Development of ultra-thin copper foil (<= 1 mu m) attached on a bilayer structure of hybrid releasing layer with good thermal resistance (<= 250 degrees C) and 12 mu m carrier for semi-conductor package substrates) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea), Nano.Material Technology Development Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT and Future Planning. (2009-0082580) and the Samsung Electronics Co., Ltd. | - |
dc.language | en | - |
dc.publisher | Electrochemical Society, Inc. | - |
dc.title | Cu Electrochemical Polishing for RDL Process of FOWLP and Effects of Cu Overburden Profiles | - |
dc.type | Article | - |
dc.relation.no | 3 | - |
dc.relation.volume | 11 | - |
dc.identifier.doi | 10.1149/2162-8777/ac56c0 | - |
dc.relation.page | 1-8 | - |
dc.relation.journal | ECS Journal of Solid State Science and Technology | - |
dc.contributor.googleauthor | Park, Kimoon | - |
dc.contributor.googleauthor | Lee, Jinhyun | - |
dc.contributor.googleauthor | Kim, Youjung | - |
dc.contributor.googleauthor | Yoon, Sanghwa | - |
dc.contributor.googleauthor | Yoo, Bongyoung | - |
dc.sector.campus | E | - |
dc.sector.daehak | 공학대학 | - |
dc.sector.department | 재료화학공학과 | - |
dc.identifier.pid | byyoo | - |
dc.identifier.article | 034001 | - |
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