198 135

Full metadata record

DC FieldValueLanguage
dc.contributor.author최정욱-
dc.date.accessioned2022-05-25T01:25:20Z-
dc.date.available2022-05-25T01:25:20Z-
dc.date.issued2020-10-
dc.identifier.citationIEEE ACCESS, v. 8, page. 195528-195540en_US
dc.identifier.issn2169-3536-
dc.identifier.urihttps://ieeexplore.ieee.org/document/9239952/-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/171156-
dc.description.abstractPhysically-addressable solid-state drives (PASSDs) are secondary storage devices that provide a physical address-based interface for a host system to directly control NAND flash memory. PASSDs overcome the shortcomings such as latency variability, resource under-utilization, and log-on-log that are associated with legacy SSDs. However, in some operating environments, the write response time significantly increases because the PASSD reports the completion of a host write command synchronously (i.e., write-through) owing to reliability problems. It contrasts asynchronous processing (i.e., write-back), which reports a completion immediately after data are received in a high-performance volatile memory subsequently used as a write buffer to conceal the operation time of NAND flash memory. Herein, we propose a new scheme that guarantees write reliability to enable a reliable asynchronous write operation in PASSD. It is designed to use a large-granularity mapping table for minimizing the memory requirements and performing internal operations at an idle time to avoid response delays. Results demonstrate that the proposed PASSD reduces the average write response time by up to 88% and guarantees reliability without performance degradation.en_US
dc.description.sponsorshipThis work was supported by the Samsung Electronics' University Research and Development Program (Research on Wear-Leveling Algorithm for Open-Channel SSD 2.0.).en_US
dc.language.isoenen_US
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCen_US
dc.subjectFlash translation layeren_US
dc.subjectNAND flash memoryen_US
dc.subjectopen-channel SSDen_US
dc.subjectphysically-addressable SSDen_US
dc.subjectsolid-state driveen_US
dc.titleImproving Write Performance Through Reliable Asynchronous Operation in Physically-Addressable SSDen_US
dc.typeArticleen_US
dc.relation.volume8-
dc.identifier.doi10.1109/ACCESS.2020.3033886-
dc.relation.page195528-195540-
dc.relation.journalIEEE ACCESS-
dc.contributor.googleauthorLee, Daeyong-
dc.contributor.googleauthorKwak, Jaewook-
dc.contributor.googleauthorLee, Gyeongyong-
dc.contributor.googleauthorJang, Moonseok-
dc.contributor.googleauthorJeong, Joonyong-
dc.contributor.googleauthorWang, Kexin-
dc.contributor.googleauthorChoi, Jungwook-
dc.contributor.googleauthorSong, Yong Ho-
dc.relation.code2020045465-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentSCHOOL OF ELECTRONIC ENGINEERING-
dc.identifier.pidchoij-
dc.identifier.orcidhttps://orcid.org/0000-0002-3075-8694-


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE