Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 어영선 | - |
dc.date.accessioned | 2021-05-17T05:46:50Z | - |
dc.date.available | 2021-05-17T05:46:50Z | - |
dc.date.issued | 2000-01 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 47, no. 1, page. 129-140 | en_US |
dc.identifier.issn | 1557-9646 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/162174 | - |
dc.description.abstract | A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance, CMOS device nonlinearity is simply approximated asa linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is,unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-mu m CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools, Thereby, this model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Integrated circuit interconnections | en_US |
dc.subject | crosstalk | en_US |
dc.subject | integrated circuit modelling | en_US |
dc.subject | CMOS integrated circuits | en_US |
dc.subject | VLSI | en_US |
dc.subject | integrated circuit design | en_US |
dc.subject | SPICE | en_US |
dc.subject | circuit simulation | en_US |
dc.subject | circuit CAD | en_US |
dc.subject | high-speed integrated circuits | en_US |
dc.subject | lumped-model | en_US |
dc.subject | signal-integrity | en_US |
dc.subject | distributed-model | en_US |
dc.subject | effective-capacitance | en_US |
dc.subject | effective-resistance | en_US |
dc.subject | interconnects | en_US |
dc.title | A New On-Chip Interconnect Crosstalk Model and Experimental Verification for CMOS VLSI Circuit Design | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/16.817578 | - |
dc.relation.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.contributor.googleauthor | Eo, Yungseon | - |
dc.contributor.googleauthor | Eisenstadt, W.R. | - |
dc.contributor.googleauthor | Jeong, Ju Young | - |
dc.contributor.googleauthor | Kwon, Oh-Kyong | - |
dc.relation.code | 2009203864 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | eo | - |
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