Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 어영선 | - |
dc.date.accessioned | 2021-02-16T05:31:25Z | - |
dc.date.available | 2021-02-16T05:31:25Z | - |
dc.date.issued | 2001-06 | - |
dc.identifier.citation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 9, issue. 3, page. 450-460 | en_US |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.issn | 1557-9999 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/abstract/document/929579 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/158372 | - |
dc.description.abstract | A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented, Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system, The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure, The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions, The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D held-solver-based results within 5% error. | en_US |
dc.description.sponsorship | This work was supported by the Center for Electronic Packaging Materials, Korea Science and Engineering Foundation. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Crosstalk | en_US |
dc.subject | interconnect capacitance | en_US |
dc.subject | multilayer | en_US |
dc.subject | shielding effect | en_US |
dc.subject | signal delay | en_US |
dc.subject | VLSI interconnects | en_US |
dc.title | Fast and Accurate Quasi-3-Dimensional Capacitance Determination of MultiLayer VLSI Interconnects | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/92.929579 | - |
dc.relation.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.contributor.googleauthor | Jin, Woojin | - |
dc.contributor.googleauthor | Eo, Yungseon | - |
dc.contributor.googleauthor | Eisenstadt, W.R. | - |
dc.contributor.googleauthor | Shim, J. | - |
dc.relation.code | 2009203903 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | eo | - |
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