New Programmable 2D FFT Processor Design

Abstract

In this paper, the architecture and the implementation of a new programmable a 2~214 point complex fast fourier transform(FFT) processor system are presented. The processor can perform 8K-point ,4K-point ,and 2K-point FFT within 661.5㎲, 341.4㎲, 123.1㎲, respectively, by using a 96.8㎒ clock. This rate is good enough to process OFDM symbols. This architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs [3]. Proposed FFT processor uses mixed radix-2 and radix-4 processing blocks to reduce the number of multiplications and additions. Butterfly circuit is improved to make it faster. The architecture has been modeled by using the VHDL and logic synthesis has been performed by using Hynix 0.35㎛ standard cell library.