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Effects of Grain Size on the Electrical Characteristics of Three-Dimensional NAND Flash Memory Devices

Title
Effects of Grain Size on the Electrical Characteristics of Three-Dimensional NAND Flash Memory Devices
Author
김태환
Keywords
Vertical NAND Flash Memory; Polysilicon Channel; Charge Trapping Layer; Threshold Voltage Shift
Issue Date
2019-10
Publisher
AMER SCIENTIFIC PUBLISHERS
Citation
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 19, no. 10, Page. 6202-6205
Abstract
Polysilicon is commonly used as the channel in three-dimensional (3D) NAND flash memory devices. However, degradation of device performance due to grain boundary traps in the channel is a major issue. The saturation on-current level, threshold voltage (V-th), and electron density of 3D NAND flash memory devices with randomly generated grain boundaries were investigated by using three-dimensional technology computer-aided design (TCAD) simulation. The device performance tended to degrade with an increasing number of grains, and the direction of the grains significantly affected the device performance. The large decrease in the electron density of the channel region due to the direction of the grains can be explained according to the formation of the depletion region.
URI
https://www.ingentaconnect.com/content/asp/jnn/2019/00000019/00000010/art00039;jsessionid=6jqqbc3halnnf.x-ic-live-01https://repository.hanyang.ac.kr/handle/20.500.11754/154664
ISSN
1533-4880; 1533-4899
DOI
10.1166/jnn.2019.17015
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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